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参数资料
| 型号： | AD73460BB-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 24-BIT, 26 MHz, OTHER DSP, PBGA119 |
| 封装： | PLASTIC, CHIP SCALE, BGA-119 |
| 文件页数： | 30/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460BB-80 |
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REV. 0
AD73460
–30–
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 19. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow
enough room in your system to fit the EZ-ICE probe onto the
14-pin connector.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 19. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion
—
you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
×
0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
PM, DM, BM, IOM, and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst-case
device timing requirements and switching characteristics as
specified in the DSP
’
s data sheet. The performance of the
EZ-ICE
may approach published worst-case specification for
some memory access timing requirements and switching
characteristics.
Note:
If your target does not meet the worst-case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency.
Depending on the severity of the specification violation, you
may have trouble manufacturing your system as DSP compo-
nents statistically vary in switching characteristic and timing
requirements within published limits.
Restriction:
All memory strobe signals on the AD73460 (
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
, and
IOMS
) used in your target
system must have 10 k
pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE
board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE
board:
EZ-ICE
emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
RESET
signal.
EZ-ICE
emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
BR
signal.
EZ-ICE
emulation ignores
RESET
and
BR
when single-
stepping.
EZ-ICE
emulation ignores
RESET
and
BR
when in Emulator
Space (DSP halted).
EZ-ICE
emulation ignores the state of target
BR
in certain
modes. As a result, the target system may take control of the
DSP
’
s external memory bus
only
if bus grant (
BG
) is asserted
by the EZ-ICE
board
’
s DSP.
ANALOG FRONT END (AFE) INTERFACING
The AFE section of the AD73460 features six input channels
each with 16-bit linear resolution. Connectivity to the AFE
section from the DSP is uncommitted thus allowing the user the
flexibility of connecting in the mode or configuration of their
choice. This section will detail several configurations
—
with no
extra AFE channels configured and with an extra AFE section
configured (using an external AD73360 AFE).
DSP SPORT TO AFE INTERFACING
The SCLK, SDO, SDOFS, SDI, and SDIFS must be connected
to the SCLK, DR, RFS, DT, and TFS pins of the DSP respec-
tively. The SE pin may be controlled from a parallel output pin
or flag pin such as FL0
–
2 or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. For consistent performance the SE pin should
be synchronized to the rising edge of the AMCLK using a cir-
cuit similar to that of Figure 23. The
ARESET
pin may be
connected to the system hardware reset structure or it may also
be controlled using a dedicated control line. In the event of
tying it to the global system reset, it is necessary to operate the
device in mixed mode, which allows a software reset, otherwise
there is no convenient way of resetting the device.
TFS
DT
SCLK
DR
RFS
DSP
SECTION
AFE
SECTION
SDIFS
SDI
SCLK
SDO
SDOFS
FL0
FL1
ARESET
SE
Figure 20. DSP to AD73460 AFE Connection
相关PDF资料 |
PDF描述 |
|---|---|
| AD73460 | Six-Input Channel Analog Front End |
| AD73460BB-40 | Six-Input Channel Analog Front End |
| AD7346B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD5011 | M5100-033-0008 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD734AN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD734ANZ | 功能描述:IC MULT/DIV 4-QUADRANT 14-DIP RoHS:是 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
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