- 您现在的位置：买卖IC网 > PDF目录373897 > AD73460BB-80 (ANALOG DEVICES INC) Six-Input Channel Analog Front End PDF资料下载
参数资料
| 型号： | AD73460BB-80 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | 24-BIT, 26 MHz, OTHER DSP, PBGA119 |
| 封装： | PLASTIC, CHIP SCALE, BGA-119 |
| 文件页数： | 8/32页 |
| 文件大小： | 290K |
| 代理商： | AD73460BB-80 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
REV. 0
AD73460
–8–
PIN FUNCTION DESCRIPTIONS
1
Mnemonic
VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REFOUT
REFCAP
Function
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 3.
Analog Input to the Negative Terminal of Input Channel 3.
Analog Input to the Positive Terminal of Input Channel 4.
Analog Input to the Negative Terminal of Input Channel 4.
Analog Input to the Positive Terminal of Input Channel 5.
Analog Input to the Negative Terminal of Input Channel 5.
Analog Input to the Positive Terminal of Input Channel 6.
Analog Input to the Negative Terminal of Input Channel 6.
Buffered Reference Output, which has a nominal value of 1.25 V.
A Bypass Capacitor to AGND2 of 0.1
μ
F is required for the on-chip reference. The capacitor should be fixed
to this pin. This pin can be overdriven by an external reference if required.
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Ground/Substrate Connection
Digital Power Supply Connection
Active Low Reset Signal. This input resets the analog front end of the AD73460, resetting the control registers and
clearing the digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the AFE. It is used to clock data or
control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency
of the master clock (MCLK) divided by an integer number
—
this integer number being the product of the
external master clock rate divider and the serial clock rate divider.
Master Clock Input of the analog front end. MCLK is driven from an external clock signal.
Serial Data Output of the AD73460. Both data and control information may be output on this pin and are clocked
on the positive edge of SCLK2. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK2. SDOFS is in
three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before
the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK2 and is ignored when SE
is low.
Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK2. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are
at their original values (before SE was brought low); however, the timing counters and other internal registers are
at their reset values.
(Input) Processor Reset Input
(Input) Bus Request Input
(Output) Bus Grant Output
(Output) Bus Grant Hung Output
(Output) Data Memory Select Output
(Output) Program Memory Select Output
(Output) Memory Select Output
(Output) Byte Memory Select Output
(Output) Combined Memory Select Output
(Output) Memory Read Enable Output
AVDD
AGND
DGND
DVDD
ARESET
SCLK2
MCLK
SDO
SDOFS
SDIFS
SDI
SE
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
相关PDF资料 |
PDF描述 |
|---|---|
| AD73460 | Six-Input Channel Analog Front End |
| AD73460BB-40 | Six-Input Channel Analog Front End |
| AD7346B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD5011 | M5100-033-0008 |
| AD5011B | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7346ASTZ | 制造商:Analog Devices 功能描述: |
| AD7346ASTZ-RL | 功能描述:IC ANALOG FRONT END 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD7346B | 制造商:AD 制造商全称:Analog Devices 功能描述:2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| AD734AN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD734ANZ | 功能描述:IC MULT/DIV 4-QUADRANT 14-DIP RoHS:是 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。