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参数资料
| 型号： | AD7441BRTZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT W/DIFF INP SOT-23-8 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 |
| 供应商设备封装： | SOT-23-8 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 其它名称： | AD7441BRTZ-REEL7DKR |
AD7441/AD7451
Rev. D | Page 18 of 24
MODES OF OPERATION
The operating mode of the AD7441/AD7451 is selected by
controlling the logic state of the CS signal during a conversion.
There are two operating modes: normal mode and power-down
mode. The point at which CS is pulled high after the conversion
is initiated determines whether the part enters power-down mode.
Similarly, if already in power-down, CS controls whether the
device returns to normal operation or remains in power-down.
These modes provide flexible power management options that
can optimize the power dissipation/throughput rate ratio for
differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7441/AD7451 remaining fully powered up all the time.
Figure 29 shows the general diagram of the operation of the
AD7441/AD7451 in this mode. The conversion is initiated
on the falling edge of CS (see the
section). To
ensure that the part remains fully powered up,
CS must remain
low until at least 10 SCLK falling edges elapse after the falling
edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part remains pow-
ered up, however the conversion is terminated and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the complete conversion
result. CS can idle high until the next conversion or can idle
low until sometime prior to the next conversion. Once a data
transfer is complete—that is, when SDATA has returned to
three-state—another conversion can be initiated after the
quiet time, tQUIET, elapses again bringing CS low.
110
CS
SCLK
SDATA
16
4 LEADING ZEROS + CONVERSION RESULT
0
31
53
-0
29
Figure 29. Normal Mode Operation
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered
down between each conversion or a series of conversions can
be performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of conversions. When the AD7441/AD7451 are in
power-down mode, all analog circuitry is powered down.
For the AD7441/AD7451 to enter power-down mode, the
conversion process must be interrupted by bringing CS high
anywhere after the second falling edge of SCLK and before
the 10th falling edge of SCLK, as shown in
.
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
three-state enabled is never greater than t8 (see the
section). If
CS is brought high before the second
SCLK falling edge, the part remains in normal mode and does
not power down. This avoids accidental power-down due to
glitches on the CS line.
To exit power-down mode and power up the AD7441/AD7451
again, a dummy conversion is performed. On the falling edge
of CS, the device begins to power up and continues to do so
as long as CS is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after 1 μs has elapsed and,
as shown in
, valid data results from the next
conversion.
1
10
SCLK
SDATA
THREE-STATE
2
CS
0
31
53
-0
30
Figure 30. Entering Power-Down Mode
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