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参数资料
| 型号： | AD7490BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 16CHAN 28TSSOP |
| 产品变化通告： | IDD Specification Change 17/Jun/2009 |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 16 个单端，单极 |
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AD7490
Data Sheet
Rev. D | Page 22 of 28
SERIAL INTERFACE
Figure 27 shows the detailed timing diagram for serial interfacing
to the AD7490. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7490 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14th SCLK falling edge, as shown in
Figure 27 at point B, except when the write is to the Shadow
register, in which case the track-and-hold does not return to
track until the rising edge of CS, that is, Point C in Figure 28.
On the 16th SCLK falling edge, the DOUT line goes back into
three-state (assuming the WEAK/TRI bit is set to 0). Sixteen
serial clock cycles are required to perform the conversion
process and to access data from the AD7490. The 12 bits of
conversion data are preceded by the four channel address bits,
ADD3 to ADD0, identifying which channel the conversion
result corresponds to. CS going low allows the ADD3 address
bit to be read in by the microprocessor or DSP. The remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges, beginning with the second address bit,
ADD2. Thus, the first SCLK falling edge on the serial clock has
the ADD3 address bit provided and also clocks out address bit
ADD2. The final bit in the data transfer is valid on the 16th
falling edge, having being clocked out on the previous (15th)
falling edge.
Writing information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, that is, the WRITE bit, has been set to 1. If the control
register is programmed to use the Shadow register, writing
information to the Shadow register takes place on all 16 SCLK
falling edges in the next serial transfer (see Figure 28). The
Shadow register is updated upon the rising edge of CS, and the
track-and-hold begins to track the first channel selected in the
sequence.
02
69
1-
02
6
SCLK
DOUT
DIN
CS
WRITE
SEQ
ADD3
ADD2
ADD1
ADD0
DONTC
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
B
t2
t3b
t3
1
2
3
4
5
6
13
14
15
16
t9
t10
t8
t4
t7
t6
t5
t11
tQUIET
tCONVERT
THREE-
STATE
THREE-
STATE ADD3
FOUR IDENTIFICATION BITS
Figure 27. Serial Interface Timing Diagram
0
269
1-
0
27
SCLK
DOUT
DIN
CS
t2
t3
t9
t10
t8
t4
t7
t6
t5
t11
tCONVERT
THREE-
STATE
THREE-
STATE ADD3
FOUR IDENTIFICATION BITS
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
C
1
2
3
4
5
6
13
14
15
16
VIN0VIN1VIN2VIN3VIN4VIN5VIN13
VIN14
VIN15
Figure 28. Writing to Shadow Register Timing Diagram
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