参数资料
| 型号： | AD7606BSTZ-4RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC DAS W/ADC 16BIT 64LQFP |
| 设计资源： | Layout Considerations for an Expandable Multichannel Simultaneous Sampling Data Acquisition System Based on AD7606 (CN0148) |
| 标准包装： | 1 |
| 类型： | 数据采集系统（DAS），ADC |
| 分辨率（位）： | 16 b |
| 采样率（每秒）： | 200k |
| 数据接口： | DSP，MICROWIRE?，并联，QSPI?，串行，SPI? |
| 电压电源： | 模拟和数字 |
| 电源电压： | 2.3 V ~ 5.25 V，4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 标准包装 |
| 其它名称： | AD7606BSTZ-4RLDKR |
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Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. C | Page 13 of 36
AD7606-4
TOP VIEW
(Not to Scale)
64 63 62
61
60 59 58
57
V
1G
ND
56 55 54 53 52 51 50 49
V3
AG
ND
V4
AG
ND
V2
V1
PIN 1
AG
ND
AG
ND
V
2G
ND
AG
ND
AG
ND
V
3G
ND
V
4G
ND
AG
ND
AG
ND
DB13
DB12
DB11
DB14/
HBE
N
V
DRI
V
E
DB1
17 18
19
20
21 22 23
24 25
AG
ND
26
27 28 29 30 31 32
DB2
DB3
DB4
DB5
DB6
DB7/
D
O
UT
A
DB9
DB10
DB8/
D
O
UT
B
AGND
AVCC 1
3
4
FRSTDATA
7
6
5
OS 2
2
8
9
10
12
13
14
15
16
11
DB0
BUSY
CONVST B
CONVST A
RANGE
RESET
RD/SCLK
CS
PAR/SER/BYTE SEL
OS 1
OS 0
STBY
DECOUPLING CAP PIN
DATA OUTPUT
POWER SUPPLY
ANALOG INPUT
GROUND PIN
DIGITAL OUTPUT
DIGITAL INPUT
REFERENCE INPUT/OUTPUT
DB15/BYTE SEL
REFIN/REFOUT
48
46
45
42
43
44
47
41
40
39
37
36
35
34
33
38
AGND
AVCC
REFGND
REFCAPA
AGND
REFCAPB
REFGND
REGCAP
AVCC
REF SELECT
08479-
010
Figure 10. AD7606-4 Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Type1
Mnemonic
Description
AD7606
AD7606-6
AD7606-4
1, 37, 38,
48
P
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to
the internal front-end amplifiers and to the ADC core. These supply pins
should be decoupled to AGND.
2, 26, 35,
40, 41, 47
P
AGND
Analog Ground. These pins are the ground reference points for all analog
circuitry on the AD7606. All analog input signals and external reference
signals should be referred to these pins. All six of these AGND pins should
connect to the AGND plane of a system.
5, 4, 3
DI
OS [2:0]
Oversampling Mode Pins. Logic inputs. These inputs are used to select the
oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control
bit. See the Digital Filter section for more details about the oversampling
mode of operation and Table 9 for oversampling bit decoding.
6
DI
PAR/SER/
BYTE SEL
PAR/SER/
BYTE SEL
PAR/SER/
BYTE SEL
Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to
a logic low, the parallel interface is selected. If this pin is tied to a logic high,
the serial interface is selected. Parallel byte interface mode is selected when
this pin is logic high and DB15/BYTE SEL is logic high (see Table 8).
In serial mode, the RD/SCLK pin functions as the serial clock input. The
DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When
the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to
ground.
In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select
the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN
pin. DB[7:0] transfer the 16-bit conversion results in two RD operations,
with DB0 as the LSB of the data transfers.
7
DI
STBY
Standby Mode Input. This pin is used to place the AD7606/AD7606-6/
AD7606-4 into one of two power-down modes: standby mode or shutdown
mode. The power-down mode entered depends on the state of the RANGE
pin, as shown in Table 7. When in standby mode, all circuitry, except the on-
chip reference, regulators, and regulator buffers, is powered down. When
in shutdown mode, all circuitry is powered down.
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