参数资料
| 型号： | AD7641BSTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 2MSPS SAR 48-LQFP |
| 产品培训模块： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 标准包装： | 2,000 |
| 位数： | 18 |
| 采样率（每秒）： | 2M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 92mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | EVAL-AD7641CBZ-ND - BOARD EVALUATION FOR AD7641 |
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AD7641
Rev. 0 | Page 20 of 28
POWER SUPPLY
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
The AD7641 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in
CONVERSION CONTROL
The AD7641 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in
Power Sequencing
Figure 29. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
complete. The
The AD7641 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
very insensitive to power supply variations over a wide
frequency range, as shown in Figure 28.
65.0
45.0
1
10000
FREQUENCY (MHz)
P
S
RR
(
d
B)
0
476
1-
0
29
10
100
1000
62.5
60.0
57.5
55.0
52.5
50.0
47.5
INT REF
EXT REF
Figure 28. PSRR vs. Frequency
Power-Up
At power-up, or returning to operational mode from the power-
down mode (PD = high), the AD7641 engages an initialization
process. During this time, the first 128 conversions should be
ignored or the RESET input could be pulsed to engage a faster
initialization process. Refer to the Digital Interface section for
RESET and timing details.
A simple power-on reset circuit, as shown in Figure 23, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7641 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
CNVST signal operates independently of CS and
RD signals.
047
61-
030
BUSY
MODE
CONVERT
ACQUIRE
CONVERT
CNVST
t1
t2
t4
t3
t5
t6
t7
t8
Figure 29. Basic Conversion Timing
CNVST
For optimal performance, the rising edge of
should not
occur after the maximum CNVST low time, t1, or until the end
of conversion.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 23.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 23.
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