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参数资料
| 型号： | AD7664ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT UNIPOLAR 48-LFCSP |
| 标准包装： | 13 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 570k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 115mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个伪差分，单极 |
| 配用： | EVAL-AD7664CBZ-ND - BOARD EVALUATION FOR AD7664 |
REV. E
–6–
AD7664
Pin No.
Mnemonic
Type
Description
16
D7
DI/O
When SER/
PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the Serial Port, is used as either an external
data input or a Read Mode selection input depending on the state of EXT/
INT.
When EXT/
INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/
INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground.
21
D8
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664
provides the conversion result, MSB first, from its internal shift register. The DATA format
is determined by the logic level of OB/
2C. In Serial Mode, when EXT/INT is LOW, SDOUT is
valid on both edges of SCLK.
In Serial Mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
22
D9
DI/O
When SER/
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data
or SCLK
Output Bus.
When SER/
PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
D10
DO
When SER/
PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/
PAR is HIGH, this output, part of the Serial Port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When
a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains
HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC
is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid.
24
D11
DO
When SER/
PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is
used as an incomplete read error flag. In Slave Mode, when a data read is started and not
complete when the following conversion is complete, the current data is lost and RDERROR
is pulsed HIGH.
25–28
D[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/
PAR.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
CS is also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted.
If not used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
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