参数资料
型号: AD7664ACPZ
厂商: Analog Devices Inc
文件页数: 6/24页
文件大小: 0K
描述: IC ADC 16BIT UNIPOLAR 48-LFCSP
标准包装: 13
系列: PulSAR®
位数: 16
采样率(每秒): 570k
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 115mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
输入数目和类型: 2 个伪差分,单极
配用: EVAL-AD7664CBZ-ND - BOARD EVALUATION FOR AD7664
REV. E
–14–
AD7664
For instance, in a driver like the AD8021, with an equivalent
input noise of 2 nV/
√Hz and configured as a buffer, thus with a
noise gain of 1, the SNR degrades by 0.58 dB.
The driver needs to have a THD performance suitable to that
of the AD7664. TPC 12 gives the THD versus frequency
that the driver should preferably exceed.
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
The AD8022 could also be used where a dual version is needed
and a gain of 1 is used.
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.
Voltage Reference Input
The AD7664 uses an external 2.5 V voltage reference.
The voltage reference input REF of the AD7664 has a dynamic
input impedance; it should, therefore, be driven by a low imped-
ance source with an efficient decoupling between REF and
REFGND inputs. This decoupling depends on the choice of the
voltage reference, but usually consists of a 1
F ceramic capacitor
and a low ESR tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance. 47
F is an
appropriate value for the tantalum capacitor when used with one
of the recommended reference voltages:
The low noise, low temperature drift ADR421 and AD780
voltage references
The low power ADR291 voltage reference
The low cost AD1582 voltage reference
For applications using multiple AD7664s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference that directly affects the full-scale
accuracy, if this parameter matters. For instance, a
±15 ppm/°C
tempco of the reference changes the full scale by
±1 LSB/°C.
VREF , as mentioned in the specification table, could be increased to
AVDD – 1.85 V. The benefit here is the increased SNR obtained
as a result of this increase. Since the input range is defined in
terms of VREF, this would essentially increase the range to make it
a 0 V to 3 V input range with an AVDD above 4.85 V. The
theoretical improvement as a result of this increase in reference is
1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise,
however, the observed improvement is approximately 1 dB. The
AD780 can be selected with a 3 V reference voltage.
Power Supply
The AD7664 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and 5.25 V.
To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 5. The AD7664 is independent
of power supply sequencing and thus free from supply voltage
induced latch-up. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 9.
POWER DISSIPATION VERSUS THROUGHPUT
Operating currents are very low during the acquisition phase, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 10. This power saving depends on the
mode used. In Impulse Mode, the AD7664 automatically reduces
its power consumption at the end of each conversion phase. This
feature makes the AD7664 ideal for very low power battery-
operated applications. It should be noted that the digital interface
remains active even during the acquisition phase. To reduce the
operating digital supply currents even further, the digital inputs
need to be driven close to the power supply rails (i.e., DVDD or
DGND for all inputs except EXT/
INT, INVSYNC, INVSCLK,
RDC/SDIN, and OVDD or OGND for these last four inputs).
–50
1
PSRR
dB
INPUT FREQUENCY – kHz
1000
–60
–70
–80
100
–55
–65
–75
10
Figure 9. PSRR vs. Frequency
100k
0.1
POWER
DISSIPATION
W
SAMPLING RATE – SPS
100k
1k
10
1
100
10k
1M
10k
1k
100
10
1
0.1
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate
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