参数资料
| 型号： | AD7760BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/37页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2.5MSPS 64TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 2.5M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 958mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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AD7760
Rev. A | Page 21 of 36
INVALID DATA
MOD DATA M
MOD DATA M + 1
MOD D...
t9
t10
t20
DRDY
D[0:15]
MCLK
CS, RD/WR
t11
t19
t14
0
497
5-
0
52
Figure 45. AD7760 Modulator Output Mode (CDIV = 0, n is odd)
In the case where n is an odd number of MCLK cycles, the
modulator data output on Pins D [15:0] is output on the rising
edge of DRDY. In this case, the modulator data should be read
on the falling edge of MCLK when DRDY is logic low. Figure 45
shows timing details to be used when reading the modulator
output data where CDIV = 0 and there is an odd number of
MCLK cycles between the rising edge of RESET and the rising
edge of SYNC. The edge of MCLK that should be used under
these conditions is illustrated in Figure 45 by arrows on the
MCLK falling edges in question.
USING THE AD7760
IN MODULATOR OUTPUT MODE
The following is the recommended sequence for powering up
and using the AD7760:
1.
Apply power.
2.
Start the clock oscillator, applying MCLK.
3.
Take RESET low for a minimum of one MCLK cycle.
4.
Wait a minimum of two MCLK cycles after the rising edge
of RESET.
5.
Write to Control Register 2 to power up the ADC and the
differential amplifier as required. The correct clock divider
(CDIV) ratio should be programmed at this time.
6.
Write to Control Register 1 to set the bypass filter bits, BYP F1
and BYP F3, and the decimation rate bits, DEC [2:0], to 0.
7.
Wait a minimum of six MCLK cycles after the rising edge
of CS has been released.
8.
Take SYNC low for a minimum of four MCLK cycles, if
required, to synchronize multiple parts.
Using this sequence results in an even number of MCLK cycles
between the rising edge of RESET and the rising edge of SYNC.
Therefore, when using this sequence with CDIV = 0, the interface
timing shown in Figure 43 should be implemented.
Note that whether the number of MCLK cycles between the
rising edge of RESET and SYNC is odd or even is irrelevant
when the AD7760 is operated with CDIV = 1.
When using the AD7760 in modulator output mode, the offset,
gain, and overrange registers are not operational. The only
registers that can be used are Control Register 1 and Control
Register 2.
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