参数资料
| 型号： | AD7760BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/37页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2.5MSPS 64TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 2.5M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 958mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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AD7760
Rev. A | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
DG
ND
63
V
DR
IV
E
62
DG
ND
61
DB0
60
DB1
59
DB2
58
DB3
57
DB4
56
DB5
55
DB6
54
DB7
53
DG
ND
52
DB8
51
DB9
50
DB10
49
DB11
47
DB13
46
DB14
45
DB15
42
DGND
43
DGND
44
VDRIVE
48
DB12
41
DVDD
40
CS
39
RD/WR
37
RESET
36
SYNC
35
DGND
34
AGND1
33
AVDD1
38
DRDY
2
MCLKGND
3
MCLK
4
AVDD2
7
AGND1
6
AVDD1
5
AGND2
1
DGND
8
DECAPA
9
REFGND
10
VREF+
12
AVDD4
13
AGND2
14
AVDD2
15
AVDD2
16
AGND2
11
AGND4
PIN 1
17
R
BI
AS
18
AG
ND
2
19
V
IN
A+
20
V
IN
A–
21
V
OU
T
A–
22
V
OU
T
A+
23
AG
ND
3
24
AV
DD
3
25
V
IN
+
26
V
IN
–
27
AV
DD
2
28
AG
ND
2
29
AG
ND
3
30
DE
CAP
B
31
AG
ND
3
32
AG
ND
3
AD7760
TOP VIEW
(Not to Scale)
0
49
75
-00
5
Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
6, 33
AVDD1
2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively)
with 100 nF and 10 μF capacitors on each pin. See the Decoupling and Layout Recommendations section
for details.
4, 14, 15, 27
AVDD2
5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors
on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the
Decoupling and Layout Recommendations section for details.
24
AVDD3
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a
100 nF capacitor. See the Decoupling and Layout Recommendations section for details.
12
AVDD4
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor
in series with a 10 Ω resistor.
7, 34
AGND1
Power Supply Ground for Analog Circuitry Powered by AVDD1.
5, 13, 16, 18, 28
AGND2
Power Supply Ground for Analog Circuitry Powered by AVDD2.
23, 29, 31, 32
AGND3
Power Supply Ground for Analog Circuitry Powered by AVDD3.
11
AGND4
Power Supply Ground for Analog Circuitry Powered by AVDD4.
9
REFGND
Reference Ground. Ground connection for the reference voltage.
41
DVDD
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF
capacitor.
44, 63
VDRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both of these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43,
53, 62, 64
DGND
Ground Reference for Digital Circuitry.
19
VINA+
Positive Input to Differential Amplifier.
20
VINA
Negative Input to Differential Amplifier.
21
VOUTA
Negative Output from Differential Amplifier.
22
VOUTA+
Positive Output from Differential Amplifier.
25
VIN+
Positive Input to the Modulator.
26
VIN
Negative Input to the Modulator.
10
VREF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4).
See the Reference Voltage Filtering section for more details.
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND.
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