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参数资料
| 型号： | AD7763BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 625KSPS 64-TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 625k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 955.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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Data Sheet
AD7763
Rev. B | Page 21 of 32
Sampling Switch SS1 and Sampling Switch SS3 are driven by ICLK,
whereas Sampling Switch SS2 and Sampling Switch SS4 are driven
by ICLK. When ICLK is high, the analog input voltage is connected
to CS1. On the falling edge of ICLK, the SS1 and SS3 switches open,
and the analog input is sampled on CS1. Similarly, when ICLK
is low, the analog input voltage is connected to CS2. On the
rising edge of ICLK, the SS2 and SS4 switches open, and the
analog input is sampled on CS2.
Capacitor CPA, Capacitor CPB1, and Capacitor CPB2 represent
parasitic capacitances that include the junction capacitances
associated with the MOS switches.
Table 11. Equivalent Component Values
Mode
CS1
CS2
CPA
CPB1/CPB2
Normal
51 pF
12 pF
20 pF
Low Power
13 pF
12 pF
5 pF
USING THE AD7763
Following is the recommended sequence for powering up and
using the AD7763.
1. Apply power.
2. Start clock oscillator, applying MCLK.
3. Take RESET low for a minimum of 1 MCLK cycle.
4. Wait a minimum of 2 MCLK cycles after RESET has been
released.
5. Write to Control Register 2 to power up the ADC and the
differential amplifier, as required.
6. Write to Control Register 1 to set up the output data rate.
7. In circumstances where multiple parts are being
synchronized, a SYNC pulse must be applied to the parts;
otherwise, no SYNC pulse is required.
The following are conditions for applying the SYNC pulse:
The issuing of a SYNC pulse to the part must not coincide
with a write to the part.
The SYNC pulse should be applied a minimum
of 2.5 ICLK cycles after the FSI signal for the previous write
to the part has returned to logic high.
Ensure that the SYNC pulse is taken low for a minimum of
2.5 ICLK cycles.
Data can now be read from the part using the default filter,
offset, gain, and overrange threshold values. The conversion
data read is not valid, however, until the settling time of the
filter has passed. When this has occurred, the DVALID bit read
is set, indicating that the data is indeed valid.
The user can then download a user-defined filter, if required
(see Downloading a User-Defined Filter). Values for gain, offset,
and overrange threshold registers can also be written or read at
this stage.
BIAS RESISTOR SELECTION
The AD7763 requires a resistor to be connected between the
RBIAS pin and AGND. The value for this resistor is dependent on
the reference voltage being applied to the device. The resistor
value should be selected to give a current of 25 A through the
resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 kΩ; for a 4.096 V reference voltage, the
correct resistor value is 160 kΩ.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7764 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7764_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit, 312 kSPS, 109 dB ヒ-ツ ADC with On-Chip Buffers and Serial Interface |
| AD7764BRUZ | 功能描述:IC ADC 24BIT S/D 312KSPS 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| AD7764BRUZ-REEL7 | 功能描述:IC ADC 24BIT S/D 312KSPS 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7765 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
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