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参数资料
| 型号： | AD7763BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 625KSPS 64-TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 625k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 955.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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AD7763
Data Sheet
Rev. B | Page 14 of 32
THEORY OF OPERATION
The AD7763 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
Due to the high oversampling rate, which spreads the quanti-
zation noise from 0 to f
ICLK, the noise energy contained in the
band of interest is reduced (see Figure 23). To further reduce
quantization noise, a high order modulator is employed to shape
the noise spectrum; thus, most of the noise energy is shifted
out of the band of interest (see Figure 24).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 25), while
also reducing the data rate from f
ICLK at the input of the filter
to f
ICLK/32 or less at the output of the filter, depending on the
decimation rate used.
Digital filtering has certain advantages over analog filtering.
It does not introduce significant noise or distortion and can
be made perfectly linear phase.
The AD7763 employs three finite impulse response (FIR) filters
in series. By using different combinations of decimation ratios
and filter selection, data can be obtained from the AD7763 at
four different data rates. The first filter receives data from the
modulator at ICLK
MHz, where it is decimated × 4 to output
data at (ICLK/4)
MHz.
The second filter allows the decimation rate to be chosen from
8× to 32×. The third filter has a fixed decimation rate of 2×, is
user programmable, and has a default configuration (see the
Programmable FIR Filter section). This filter can be bypassed.
Table 6 shows some characteristics of the default filter. The group
delay of the filter is defined as the delay to the center of the
impulse response and is equal to the computation plus filter
delays. The delay until valid data is available (the DVALID status bit
is set) is equal to 2× the filter delay plus the computation delay.
05
47
6-
0
2
4
QUANTIZATION NOISE
fICLK/2
BAND OF INTEREST
Figure 23. Σ-Δ ADC, Quantization Noise
05
47
6-
02
5
fICLK/2
NOISE SHAPING
BAND OF INTEREST
Figure 24. Σ-Δ ADC, Noise Shaping
05
47
6-
01
2
fICLK/2
BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY
Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency
Table 6. Configuration With Default Filter
ICLK
Frequency
Filter 1
Filter 2
Filter 3
Data State
Computation
Delay
Filter
Delay
Pass Band
Bandwidth
Output Data Rate
(ODR)
20 MHz
4×
2×
Fully filtered
1.775 μs
44.4 μs
250 kHz
625 kHz
20 MHz
4×
8×
Bypassed
Partially
filtered
2.6 μs
10.8 μs
140.625 kHz
625 kHz
20 MHz
4×
8×
2×
Fully filtered
2.25 μs
87.6 μs
125 kHz
312.5 kHz
20 MHz
4×
16×
Bypassed
Partially
filtered
4.175 μs
20.4 μs
70.3125 kHz
312.5 kHz
20 MHz
4×
16×
2×
Fully filtered
3.1 μs
174 μs
62.5 kHz
156.25 kHz
20 MHz
4×
32×
Bypassed
Partially
filtered
7.325 μs
39.6 μs
35.156 kHz
156.25 kHz
20 MHz
4×
32×
2×
Fully filtered
4.65 μs
346.8 μs
31.25 kHz
78.125 kHz
12.288 MHz
4×
8×
2×
Fully filtered
3.66 μs
142.6 μs
76.8 kHz
192 kHz
12.288 MHz
4×
16×
2×
Fully filtered
5.05 μs
283.2 μs
38.4 kHz
96 kHz
12.288 MHz
4×
32×
Bypassed
Partially
filtered
11.92 μs
64.45 μs
21.6 kHz
96 kHz
12.288 MHz
4×
32×
2×
Fully filtered
7.57 μs
564.5 μs
19.2 kHz
48 kHz
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| AD7764_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit, 312 kSPS, 109 dB ヒ-ツ ADC with On-Chip Buffers and Serial Interface |
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