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参数资料
| 型号： | AD7763BSVZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 625KSPS 64-TQFP |
| 标准包装： | 1,500 |
| 位数： | 24 |
| 采样率（每秒）： | 625k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 955.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP-EP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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Data Sheet
AD7763
Rev. B | Page 15 of 32
AD7763 INTERFACE
READING DATA USING THE SPI INTERFACE
The timing diagram in Figure 2 shows how the AD7763 transmits
its conversion results using the SPI-compatible serial interface.
The data being read from the AD7763 is clocked out using the
serial clock output, SCO. The SCO frequency is dependent on
the state of the serial clock output rate pin, SCR, and the clock
divider mode chosen by the state of the clock divider pin, CDIV
(see the Clocking the AD7763 section). Table 7 shows both the
SCO frequency and the ICLK frequency for the AD7763, resulting
from the states of both the CDIV and SCR pins.
Table 7. SCO Frequency
Clock Divide
Mode
CDIV
SCR
SCO
Frequency
ICLK
Frequency
Divide by 1
1
0
MCLK
1
MCLK
Divide by 2
0
MCLK/2
1
MCLK1
MCLK/2
1
In decimate × 32 mode, when CDIV = 0 and SCR = 1, FSO pulses low for
32 SCO clock cycles, as shown in Figure 2. For all other combinations of CDIV
and SCR in decimate × 32 mode, FSO is continuously low.
An active low pulse of one SCO period on the data-ready output,
DRDY, indicates a new conversion result is available at the
AD7763 serial data output, SDO.
Each bit of the new conversion result is clocked onto the SDO
line on the rising SCO edge and is valid on the falling SCO edge
(for SCP = 0). The conversion result spans 32 SCO clock cycles
and consists of 24 data bits in twos complement form, followed
by 7 status bits.
D6
D5
D4
D3
D2
D1
D0
ADR2
ADR1
ADR0
DVALID
OVR
LPWR
FILTER_OK
The conversion result output on the SDO line is framed by the
frame synchronization output, FSO, which is sent logic low for
32 SCO cycles following the rising edge of the DRDY signal.
Note that the SDO line is in three-state for one clock cycle
before the FSO signal returns to logic high, which means that
only 31 actual data bits are output in each conversion.
The first three status bits, ADR[2:0], are the device address bits.
The DVALID bit is asserted when the data being clocked out on
the SDO line is valid. Table 19 contains descriptions of the other
status bits: OVR, LPWR, and FILTER_OK.
There is an exception to the behavior of FSO when the AD7763
operates in decimate × 32 mode (see Endnote 1 of Table 7). If SCR
and CDIV are chosen so that the SCO frequency output has the
capability to clock through only 32 SCO cycles before the MSB
of the next conversion result is output, then FSO stays logic low
continuously.
The AD7763 also features a serial data latch output, SDL, which
outputs a pulse every 16 data bits. The SDL output offers an
alternative framing signal for serial transfers, which require
a framing signal more frequent than every 32 bits.
SYNCHRONIZATION
The SYNC input to the AD7763 provides a synchronization
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
The SYNC function allows multiple AD7763s, operated from
the same master clock and using the same SYNC signal, to be
synchronized so that each ADC simultaneously updates its
output register.
Using a common SYNC signal to all AD7763 devices in a
system allows synchronization to occur. On the falling edge of
the SYNC signal, the digital filter sequencer is reset to 0. The
filter is held in reset state until a rising edge of the SCO senses
SYNC high. Thus, to perform a synchronization of devices, a
SYNC pulse of a minimum of 2.5 ICLK cycles in length can be
applied, synchronous to the falling edge of SCO. On the first
rising edge of SCO after SYNC goes logic high, the filter is taken
out of reset, and the multiple parts gather input samples
synchronously.
Following a SYNC, the digital filter needs time to settle before
valid data can be read from the AD7763. The user knows there
is valid data on the SDO line by checking the DVALID status bit
(see D3 in the status bits listing) that is output with each conversion
result. The time from the rising edge of SYNC until the DVALID
bit is asserted is dependent on the filter configuration used. See the
Theory of Operation section and the figures listed in Table 6 for
details on calculating the time until DVALID is asserted.
SHARING THE SERIAL BUS
The AD7763 functionality allows up to eight devices to share
the same serial bus, SDO, depending on the decimation rate
that is chosen.
Table 8 details the maximum number of devices that can share
the same SDO line for each decimation rate (×32, ×64, ×128,
×256).
Table 8. Maximum Number of Devices Sharing SDO
Decimation Rate
SCO
(MHz)
×32
×64
×128
×256
Maximum Number of
Devices Sharing SDO
40
20
2
N/A
4
2
8
4
8
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