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参数资料
| 型号： | AD7934BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 4CH 1.5MSPS 28TSSOP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1.5M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极；2 个伪差分，单极 |
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AD7933/AD7934
Rev. B | Page 23 of 32
PARALLEL INTERFACE
The AD7933/AD7934 have a flexible, high speed, parallel
interface. This interface is 10 bits (AD7933) or 12 bits (AD7934)
wide and is capable of operating in either word (W/B tied high)
or byte (W/B tied low) mode. The CONVST signal is used to
initiate conversions and, when operating in autoshutdown or
autostandby mode, it is used to initiate power-up.
A falling edge on the CONVST signal is used to initiate
conversions, and it also puts the ADC track-and-hold into
track. Once the CONVST signal goes low, the BUSY signal goes
high for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 10 bits or 12 bits of
conversion data. When power supplies are first applied to the
device, a rising edge on CONVST is necessary to put the track-
and-hold into track. The acquisition time of 125 ns minimum
must be allowed before CONVST is brought low to initiate a
conversion. The ADC then goes into hold on the falling edge of
CONVST and back into track on the 13th rising edge of CLKIN
after this (see Figure 34). When operating the device in
autoshutdown or autostandby mode, where the ADC powers
down at the end of each conversion, a rising edge on the
CONVST signal is used to power up the device.
t2
t3
t20
t14
t11
t9
t13
t12
t10
tCONVERT
tACQUISITION
tQUIET
t1
12
3
4
5
12
13
14
B
A
DATA
OLD DATA
DB0 TO DB11
RD
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
THREE-STATE
WITH CS AND RD TIED LOW
03
713
-00
4
Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)
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