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| 型号： | AD7934BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 4CH 1.5MSPS 28TSSOP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1.5M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极；2 个伪差分，单极 |
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AD7933/AD7934
Rev. B | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W/B
DB0
DB1
DB4
DB3
DB2
VDD
VIN2
VIN1
VIN0
CS
AGND
VREFIN/VREFOUT
DB5
DB6
DB7
DB9
DGND
VDRIVE
RD
WR
CONVST
DB10
DB8/HBEN
DB11
BUSY
CLKIN
VIN3
TOP VIEW
(Not to Scale)
AD7933/
AD7934
03
71
3-
0
6
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to AGND
with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
2
W/B
Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from
the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11. When W/B
is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin
DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off unused data lines to
DGND.
3 to 10
DB0 to DB7
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow
programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and
DB1) are always 0, and the LSB of the conversion result is available on DB2.
11
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at VDD but
should never exceed VDD by more than 0.3 V.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this pin
to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
13
DB8/HBEN
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of
data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device, DB4
and DB5 contain the ID of the channel to which the conversion result corresponds (see the channel address bits in
Table 10). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all 0s.
Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining six bits are
conversion data.
14 to
16
DB9 to
DB11
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the VDRIVE input.
17
BUSY
Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high following
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode
18
CLKIN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7933/AD7934 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.
19
CONVST
Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to
hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following power-
down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up
the device.
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