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参数资料
| 型号： | AD7980BCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 1MSPS SAR 10LFCSP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 其它名称： | AD7980BCPZ-RL7DKR |
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Data Sheet
AD7980
Rev. C | Page 21 of 28
CHAIN MODE, WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7980s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multi-converter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7980s is shown in
Figure 39, and the corresponding timing is given in Figure 40.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the Busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7980 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7980s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
06392-
023
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7980 SDO
SDI
CNV
A
SCK
AD7980 SDO
SDI
CNV
B
SCK
Figure 39. Chain Mode Without Busy Indicator Connection Diagram
06392-
024
tCONV
tCYC
tSSDISCK
tSCKL
tSCK
tHSDISC
tACQ
AQUISITION
tSSDICNV
AQUISITION
tSCKH
CONVERSION
SDOA = SDIB
tHSDICNV
SCK
CNV
SDIA = 0
SDOB
tEN
DA15
DA14
DA13
DB15
DB14
DB13
DB1
DB0
DA15
DA14
DA0
DA1
DA0
tHSDO
1
2
3
15
16
17
14
18
30
31
32
tDSDO
Figure 40. Chain Mode Without Busy Indicator Serial Interface Timing
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