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| 型号： | AD7980BCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 1MSPS SAR 10LFCSP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 其它名称： | AD7980BCPZ-RL7DKR |
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Data Sheet
AD7980
Rev. C | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
06392-
004
REF
1
VDD
2
IN+
3
IN–
4
VIO
10
SDI
9
SCK
8
SDO
7
GND
5
CNV
6
AD7980
TOP VIEW
(Not to Scale)
Figure 4. 10-Lead MSOP Pin Configuration
06392-
005
REF 1
VDD 2
IN+ 3
IN– 4
10 VIO
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE ELECTRICAL PERFORMANCES.
9 SDI
8 SCK
7 SDO
GND 5
6 CNV
AD7980
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 F capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Analog Input. It is referred to IN. The voltage range, for example, the difference between IN+ and IN, is
0 V to VREF.
4
IN
AI
Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows.
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low; if SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
EPAD
Exposed Pad. For the 10-lead QFN (LFCSP) only, connect the exposed pad to GND. This connection is not
required to meet the electrical performances.
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
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