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参数资料
| 型号： | IDT79RC32K438-233BBI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/59页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT CORE 233MHZ 416-BGA |
| 标准包装： | 40 |
| 系列： | Interprise™ |
| 处理器类型： | MIPS32 32-位 |
| 速度： | 233MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 416-BGA |
| 供应商设备封装： | 416-PBGA（27x27） |
| 包装： | 托盘 |
| 其它名称： | 79RC32K438-233BBI |
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May 25, 2004
IDT 79RC32438
◆
DMA Controller
– 10 DMA channels: two channels for PCI (PCI to Memory and
Memory to PCI), two for each Ethernet interface, two channels
for memory to memory operations, two channels for external
operations
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
address may be on any byte boundary) with arbitrary byte
length.
◆
Two Ethernet Interfaces
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Two IEEE 802.3u compatible Media Independent Interfaces
(MII) with serial management interface
– MII supports IEEE 802.3u auto-negotiation speed selection
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
◆
Universal Asynchronous Receiver Transmitter (UART)
– Compatible with the 16550 and 16450 UARTs
– Two completely separate serial channels
– Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
– 16-byte transmit and receive buffers
– Programmable baud rate generator derived from the system
clock
– Fully programmable serial characteristics:
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
– Line break generation and detection
– False start bit detection
– Internal loopback mode
◆
I2C-Bus
– Supports standard 100 Kbps mode as well as 400 Kbps fast
mode
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
slave transmitter, slave receiver
◆
Additional General Purpose Peripherals
– Two 16550-compatible serial ports
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
◆
On-chip Memory
– 4KB of high speed SRAM organized as 1K x 32 bits
– Supports burst and non-burst byte, halfword, triple-byte, and
word CPU, PCI, and DMA accesses
◆
Debug Support
– Rev. 2.6 compliant EJTAG Interface
Device Overview
The RC32438 is a member of the IDT Interprise family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32438 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
CPU Execution Core
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
set architecture (ISA).
Specifically, this device features the 4Kc CPU core developed by
MIPS Technologies Inc. (www.mips.com). This core issues a single
instruction per cycle, includes a five stage pipeline, and is optimized for
applications that require integer arithmetic. The CPU core includes 16
KB instruction and 16 KB data caches. Both caches are 4-way set asso-
ciative and can be locked on a per line basis, which allows the
programmer control over this precious on-chip memory resource. The
core also features a memory management unit (MMU). The CPU core
also incorporates an enhanced joint test access group (EJTAG) inter-
face that is used to interface to in-circuit emulator tools, providing
access to internal registers and enabling the part to be controlled exter-
nally, simplifying the system debug process. The use of this core allows
IDT's customers to leverage the broad range of software and develop-
ment tools available for the MIPS architecture, including operating
systems, compilers, and in-circuit emulators.
Double Data Rate Memory Controller
The RC32438 incorporates a high performance double data rate
(DDR) memory controller which supports both x16 and x32 memory
configurations up to 2GB. This module provides all of the signals
required to interface to both memory modules and discrete devices,
including two chip selects, differential clocking outputs and data strobes.
Memory and I/O Controller
The RC32438 uses a dedicated local memory/IO controller including
a de-multiplexed 16-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to as many as six Intel or Motorola-
style external peripherals, and the interface can be configured to
support both 8-bit and 16-bit peripherals.
DMA Controller
The DMA controller consists of 10 independent DMA channels, all of
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, appropriate for communications and
graphics systems.
PCI Interface
The PCI interface on the RC32438 is compatible with version 2.2 of
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32438 to act as a slave controller for a PCI add-in
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