参数资料
| 型号： | AD8105ABPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 304BGA |
| 标准包装： | 1 |
| 功能： | 交叉点开关 |
| 电路： | 1 x 32:16 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 电流 - 电源： | 340mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 304-BGA 裸露焊盘 |
| 供应商设备封装： | 304-BGA（31x31） |
| 包装： | 托盘 |
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AD8104/AD8105
Rev. 0 | Page 26 of 36
APPLICATIONS INFORMATION
PROGRAMMING
The AD8104/AD8105 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 192 bits can be provided to update the entire
matrix each time. The second option allows for changing the
programming of a single output via a parallel interface. The
serial option requires fewer signals, but more time (clock cycles)
for changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete programming.
Serial Programming Description
The serial programming mode uses the CLK, DATA IN, UPDATE,
and SER/PAR device pins. The first step is to assert a low on
SER/PAR in order to enable the serial programming mode. The
parallel clock WE should be held high during the entire serial
programming operation.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every falling edge of CLK.
A total of 192 bits must be shifted in to complete the program-
ming. For each of the 16 outputs, there are five bits (D0 to D4)
that determine the source of its input followed by one bit (D5)
that determines the enabled state of the output. If D5 is low
(output disabled), the five associated bits (D0 to D4) do not
matter, because no input is switched to that output. These
comprise the first 96 bits of DATA IN. The remaining 96 bits
of DATA IN should be set to zero. If a string of 96 zeros is not
suffixed to the first 96 bits of DATA IN, a certain test mode is
employed that can cause the device to draw up to 40% more
supply current.
The most significant output address data, the enable bit (D5), is
shifted in first, followed by the input address (D4 to D0) entered
sequentially with D4 first and D0 last. Each remaining output is
programmed sequentially, until the least significant output
address data is shifted in. At this point, UPDATE can be taken
low, which programs the device according to the data that was
just shifted in. The UPDATE latches are asynchronous and
when UPDATE is low, they are transparent.
If more than one AD8104/AD8105 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK, UPDATE, and SER/PAR
pins should be connected in parallel and operated as described
previously. The serial data is input to the DATA IN pin of the
first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence is 192 bits times the number of
devices in the chain.
Parallel Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a
single output at a time. Because this takes only one WE/UPDATE
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the AD8104/
AD8105. When taken low, the RESET signal only sets each
output to the disabled state. This is helpful during power-up to
ensure that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device
generally have random data, even though the RESET signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This ensures that
the programming matrix is always in a known state. From then
on, parallel programming can be used to modify a single output
or more at a time.
In similar fashion, if UPDATE is taken low after initial power-
up, the random power-up data in the shift register will be
programmed into the matrix. Therefore, in order to prevent the
crosspoint from being programmed into an unknown state, do
not apply a low logic level to UPDATE after power is initially
applied. Programming the full shift register one time to a
desired state, by either serial or parallel programming after
initial power-up, eliminates the possibility of programming the
matrix to an unknown state.
To change the programming of an output via parallel program-
ming, SER/PAR and UPDATE should be taken high. The serial
programming clock, CLK, should be left high during parallel
programming. The parallel clock, WE, should start in the high
state. The 4-bit address of the output to be programmed should
be put on A0 to A3. The first five data bits (D0 to D4) should
contain the information that identifies the input that is pro-
grammed to the output that is addressed. The sixth data bit
(D5) determines the enabled state of the output. If D5 is low
(output disabled), then the data on D0 to D4 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the WE signal. The matrix is not programmed,
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