参数资料
| 型号： | AD8105ABPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/36页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 304BGA |
| 标准包装： | 1 |
| 功能： | 交叉点开关 |
| 电路： | 1 x 32:16 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 电流 - 电源： | 340mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 304-BGA 裸露焊盘 |
| 供应商设备封装： | 304-BGA（31x31） |
| 包装： | 托盘 |
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AD8104/AD8105
Rev. 0 | Page 34 of 36
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8104/AD8105 are specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk is higher than the minimum
obtainable due to the high output currents. These currents
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8104/AD8105.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drive a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
×
=
L
XY
R
s
M
XT
10
log
20
where:
MXY is the mutual inductance of Output X to Output Y.
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing RL. The mutual
inductance can be kept low by increasing the spacing of the
conductors and minimizing their parallel length.
PCB Layout
Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.
The packaging of the AD8104/AD8105 is designed to help keep
the crosstalk to a minimum. On the BGA substrate, each pair is
carefully routed to predominately couple to each other, with
shielding traces separating adjacent signal pairs. The ball grid
array is arranged such that similar board routing can be achieved.
Only the outer two rows are used for signals, such that vias can
be used to take the input rows to a lower signal plane if desired.
The input and output signals have minimum crosstalk if they
are located between ground planes on layers above and below,
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The input and output signals surface at the input
termination resistors and the output series back-termination
resistors. To the extent possible, these signals should also be
separated as soon as they emerge from the IC package.
PCB Termination Layout
As frequencies of operation increase, the importance of proper
transmission line signal routing becomes more important. The
bandwidth of the AD8104/AD8105 is large enough that using
high impedance routing does not provide a flat in-band
frequency response for practical signal trace lengths. It is
necessary for the user to choose a characteristic impedance
suitable for the application and properly terminate the input
and output signals of the AD8104/AD8105. Traditionally, video
applications have used 75 Ω single-ended environments. RF
applications are generally 50 Ω single-ended (and board
manufacturers have the most experience with this application).
CAT-5 cabling is usually driven as differential pairs of 100 Ω
differential impedance.
For flexibility, the AD8104/AD8105 do not contain on-chip
termination resistors. This flexibility in application comes with
some board layout challenges. The distance between the termi-
nation of the input transmission line and the AD8104/AD8105
die is a high impedance stub, and causes reflections of the input
signal. With some simplification, it can be shown that these
reflections cause peaking of the input at regular intervals in
frequency, dependent on the propagation speed (VP) of the
signal in the chosen board material and the distance (d)
between the termination resistor and the AD8104/AD8105. If
the distance is great enough, these peaks can occur in-band. In
fact, practical experience shows that these peaks are not high-Q,
and should be pushed out to three or four times the desired
bandwidth in order to not have an effect on the signal. For a
board designer using FR4 (VP = 144 × 106 m/s), this means the
AD8104/AD8105 input should be placed no farther than 1.5 cm
after the termination resistors, and preferably should be placed
even closer. The BGA substrate routing inside the AD8104/
AD8105 is approximately 1 cm in length and adds to the stub
length, so 1.5 cm PCB routing equates to d = 2.5 × 102 m in the
calculations.
(
)
d
V
n
f
P
PEAK
4
1
2
×
+
=
where n = {0, 1, 2, 3, …}.
In some cases, it is difficult to place the termination close to the
AD8104/AD8105 due to space constraints, differential routing,
and large resistor footprints. A preferable solution in this case is
to maintain a controlled transmission line past the AD8104/
AD8105 inputs and terminate the end of the line. This is known
as fly-by termination. The input impedance of the AD8104/
AD8105 is large enough and stub length inside the package is
small enough that this works well in practice. Implementation
of fly-by input termination often includes bringing the signal in
on one routing layer, then passing through a filled via under the
AD8104/AD8105 input ball, then back out to termination on
another signal layer. In this case, care must be taken to tie the
reference ground planes together near the signal via if the signal
layers are referenced to different ground planes.
OPn
ONn
IPn
INn
75
AD8104/
AD8105
06
61
2-
07
2
Figure 72. Fly-By Input Termination, Grounds for the Two Transmission Lines
Shown Must be Tied Together Close to the INn Pin
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