参数资料
型号: AD9042ASTZ
厂商: Analog Devices Inc
文件页数: 22/24页
文件大小: 0K
描述: IC ADC 12BIT 41MSPS 44-TQFP
标准包装: 1
位数: 12
采样率(每秒): 41M
数据接口: 并联
转换器数目: 3
功率耗散(最大): 735mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-LQFP
供应商设备封装: 44-LQFP(10x10)
包装: 托盘
输入数目和类型: 1 个单端,双极
产品目录页面: 780 (CN2011-ZH PDF)
AD9042
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
44 43 42
41 40 39 38 37 36 35 34
32
31
30
27
28
29
33
26
25
24
23
2
3
4
7
6
5
1
8
9
10
11
NC = NO CONNECT
12 13 14
15 16 17 18 19
20 21 22
PIN 1
AD9042
TOP VIEW
(Not to Scale)
DVCC
ENCODE
GND
AIN
VOFFSET
VREF
C1
AVCC
D11
(
M
S
B
)
GN
D
GN
D
GN
D
GN
D
D10
D9
DV
CC
DV
CC
DV
CC
DV
CC
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
GND
NC
A
V
CC
A
V
CC
A
V
CC
A
V
CC
A
V
CC
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
00
55
4-
0
03
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
DVCC
5 V Power Supply (Digital). Powers output stage only.
3
ENCODE
Encode Input. Data conversion initiated on rising edge.
4
ENCODE
Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode.
5, 6
GND
Ground.
7
AIN
Analog Input.
8
VOFFSET
Voltage Offset Input. Sets mid point of analog input range. Normally tied to VREF through a 50 Ω resistor.
9
VREF
Internal Voltage Reference. Nominally 2.4 V; normally tied to VOFFSET through a 50 Ω resistor. Bypass to ground
and with 0.1 μF + 0.01 μF microwave chip capacitor.
10
C1
Internal Bias Point. Bypass to ground with a 0.01 μF capacitor.
11, 12
AVCC
5 V Power Supply (Analog).
13, 14
GND
Ground.
15, 16
AVCC
5 V Power Supply (Analog).
17, 18
GND
Ground.
19, 20
AVCC
5 V Power Supply (Analog).
21, 22
GND
Ground.
23
NC
No Connect
24
GND
Ground.
25
D0 (LSB)
Digital Output Bit (Least Significant Bit).
26 to 33
D1 to D8
Digital Output Bits.
34, 35
GND
Ground.
36, 37
DVCC
5 V Power Supply (Digital). Powers output stage only.
38, 39
GND
Ground.
40, 41
DVCC
5 V Power Supply (Digital). Powers output stage only.
42, 43
D9 to D10
Digital Output Bits.
44
D11 (MSB)
Digital Output Bit (Most Significant Bit). Output coded as twos complement.
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