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参数资料
| 型号： | AD9146-M5375-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 设计资源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| DAC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 1G |
| 数据接口： | 串行 |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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AD9146
Data Sheet
Rev. A | Page 48 of 56
When these conditions are met, the outputs of the DACs are
updated within one DAC clock cycle of each other. The timing
requirements of the input signals are shown in Figure 67.
DACCLKP(1)/
DACCLKN(1)
DACCLKP(2)/
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
DCIP(2)/
DCIN(2)
FRAMEP(2)/
FRAMEN(2)
tSKEW
tSUSYNC
tHSYNC
09691-
073
Figure 67. FIFO Rate Synchronization Signal Timing Requirements,
2× Interpolation
Figure 67 shows the synchronization signal timing with 2×
interpolation; therefore, fDCI = × fCLK. The REFCLK input is
shown to be equal to the FIFO rate. The maximum frequency at
which the device can be resynchronized in FIFO rate mode can
be expressed as
fSYNC_I = fDATA/(8 × 2N)
where N is any non-negative integer.
ADDITIONAL SYNCHRONIZATION FEATURES
Table 25 shows the required timing between the DACCLK and the
synchronization clock when synchronization is used. This timing
restriction applies to both data rate mode and FIFO rate mode.
Table 25. Synchronization Setup and Hold Times
Parameter
Min
Max
Unit
tSKEW
tDACCLK/2
+tDACCLK/2
ps
tSUSYNC
100
ps
tHSYNC
330
ps
One-Time Synchronization
When implementing the full multichip synchronization feature
(with the REFCLK and FRAME signals aligned within one DACCLK
cycle), the user may experience difficulty meeting the DACCLK to
synchronization clock timing. In this case, a one-time synchroni-
zation method can be used. Before implementing the one-time
synchronization, make sure that the synchronization signal is
locked by checking both the sync signal locked and the sync signal
lost flags (Bit 4 and Bit 5 in Register 0x06). It is also important
that synchronization not be enabled before stable REFCLK signals
are present from the FPGA or ASIC. For more information and
a detailed flowchart of the one-time synchronization feature, see
the AN-1093 Application Note, “Synchronization of Multiple
AD9122 TxDAC+ Converters.”
Sync Status Bits
When the sync locked bit (Register 0x12, Bit 6) is set, it indicates
that the synchronization logic has reached alignment. This align-
ment is determined when the clock generation state machine
phase is constant.
Alignment takes from (11 + averaging) × 64 to (11 + averaging) ×
128 DACCLK cycles. The sync locked bit can also trigger an IRQ,
as described in the Interrupt Request Operation section.
When the sync lost bit (Register 0x12, Bit 7) is set, it indicates
that a previously synchronized device has lost alignment. This
bit is latched and remains set until cleared by overwriting the
register. This bit can also trigger an IRQ, as described in the
Interrupt Request Operation section.
The sync phase readback bits (Register 0x13, Bits[7:0]) report
the current clock phase in a 6.2 format. Bits[7:2] report which
of the 64 states (0 to 63) the clock is currently in. When averaging
is enabled, Bits[1:0] provide state accuracy (for 0, , , ).
The lower two bits give an indication of the timing margin issues
that may exist. If the synchronization sampling is error free, the
fractional clock state should be 00.
Timing Optimization
The REFCLK signal is sampled by a version of the DACCLK.
If sampling errors are detected, the opposite sampling edge can
be selected to improve the sampling point. The sampling edge
can be selected by setting Register 0x10, Bit 3 (1 = rising and
0 = falling).
The synchronization logic resynchronizes when a phase change
between the REFCLK signal and the state of the clock generation
state machine exceeds a threshold. To mitigate the effects of
jitter and prevent erroneous resynchronizations, the relative
phase can be averaged. The amount of averaging is set by the
sync averaging bits (Register 0x10, Bits[2:0]) and can be set
from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as large
as possible while still meeting the allotted resynchronization
time interval. Note that, if the average synchronization sampling
result is in approximately the middle of the probability curve,
the synchronization engine can be unstable, resulting in
corrupted output.
The value of the Sync Phase Request[5:0] bits (Register 0x11,
Bits[5:0]) is the state to which the clock generation state machine
resets upon initialization. By varying this value, the timing of the
internal clocks, with respect to the REFCLK signal, can be adjusted.
Every increment of the Sync Phase Request[5:0] value advances the
internal clocks by one DACCLK cycle. This offset can be used for
two purposes: to skew the outputs of two synchronized DAC
outputs in increments of the DACCLK cycle, and to change the
relative timing between the DAC output and the sync input
(REFCLK). This may allow for a more optimal placement of the
DCI sampling point in data rate synchronization mode.
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