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参数资料
| 型号： | AD9146-M5375-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 设计资源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| DAC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 1G |
| 数据接口： | 串行 |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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AD9146
Data Sheet
Rev. A | Page 16 of 56
THEORY OF OPERATION
High performance, small size, and low power consumption
make the AD9146 a very attractive DAC for wired and wireless
communications systems. The dual digital signal path and dual
DAC structure allow an easy interface to common quadrature
modulators when designing single sideband (SSB) transmitters.
The AD9146 offers features that allow simplified synchroniza-
tion with incoming data and between multiple devices. Auxiliary
DACs are also provided on chip. The auxiliary DACs can be used
for output dc offset compensation (for LO compensation in SSB
transmitters) and for gain matching (for image rejection optimiza-
tion in SSB transmitters).
SERIAL PORT OPERATION
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing to many industry-standard
microcontrollers and microprocessors. The serial I/O is com-
patible with most synchronous transfer formats, including both
the Motorola SPI and Intel SSR protocols. The interface allows
read/write access to all registers that configure the AD9146.
Single-byte or multiple-byte transfers are supported, as well
as MSB first or LSB first transfer formats.
32
SCLK
31
SDIO
33
CS
SPI
PORT
09691-
032
Figure 25. Serial Port Interface Pins
A communication cycle with the AD9146 has two phases.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first eight SCLK rising
edges. The instruction byte provides the serial port controller
with information regarding the data transfer cycle—Phase 2 of
the communication cycle. The Phase 1 instruction byte defines
whether the upcoming data transfer is a read or write, along with
the starting register address for the first byte of the data transfer.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the device.
A logic high on the CS pin followed by a logic low resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next eight rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one or more data bytes. Registers change immediately
upon writing to the last bit of each transfer byte.
DATA FORMAT
The instruction byte contains the information shown in Table 9.
Table 9. Serial Port Instruction Byte
I7 (MSB)
I6
I5
I4
I3
I2
I1
I0 (LSB)
R/W
A6
A5
A4
A3
A2
A1
A0
R/W, Bit 7 of the instruction byte, determines whether a read
or a write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the
register that is accessed during the data transfer portion of the
communication cycle. For multibyte transfers, A6 is the starting
byte address. The remaining register addresses are generated by
the device based on the LSB_FIRST bit (Register 0x00, Bit 6).
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device and
runs the internal state machines. The maximum frequency of
SCLK is 40 MHz. All data input is registered on the rising edge
of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS)
An active low input starts and gates a communication cycle.
It allows more than one device to be used on the same serial
communications lines. When the CS pin is high, the SDIO pin
goes to a high impedance state. During the communication
cycle, the CS pin should stay low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional pin that functions as an input in
write mode and as an output in read mode. Data is written into
the device on this pin and read from the device on this pin. The
configuration of the SDIO pin is controlled by Register 0x00,
Bit 7. To enable readback of the register data, this bit must be
set to 1.
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