- 您现在的位置：买卖IC网 > PDF目录17059 > AD9148-M5375-EBZ (Analog Devices Inc)BOARD EVAL FOR AD9149, ADL5375 PDF资料下载
参数资料
| 型号： | AD9148-M5375-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 63/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9149, ADL5375 |
| 设计资源： | AD9148-M5375-EBZ Schematic AD9148-M5375-EBZ BOM AD9148-M5375-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页当前第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
AD9148
Data Sheet
Rev. B | Page 66 of 72
INTERRUPT REQUEST OPERATION
The AD9148 provides an interrupt request output signal
(Pin H4, IRQ) that can be used to notify an external host
processor of significant device events. Upon assertion of the
interrupt, the device should be queried to determine the precise
event that occurred. The IRQ pin is an open-drain, active low
output.
Pull the IRQ pin high external to the device. This pin may be
tied to the interrupt pins of other devices with open-drain outputs
to wired-OR these pins together.
Ten different event flags provide visibility into the device. These
10 flags are located in the two event flag registers (Register 0x06
and Register 0x07). The behavior of each of the event flags is
independently selected in the interrupt enable registers
(Register 0x04 and Register 0x05). When the flag interrupt
enable is active, the event flag latches and triggers an external
interrupt. When the flag interrupt is disabled, the event flag
simply monitors the source signal, and the external IRQ
remains inactive.
Figure 91 shows the IRQ-related circuitry. Figure 91 shows how the
event flag signals propagate to the IRQ output. The interupt_enable
signal represents one bit from the interrupt enable register. The
event_flag signal represents one bit from the event flag register.
The event_flag_source signal represents one of the device signals
that can be monitored such as the PLL_locked signal from the
PLL phase detector or the FIFO Warning 1 signal from the
FIFO controller.
When an interrupt enable bit is set high, the corresponding event
flag bit reflects a positively tripped (that is, latched on the rising
edge of the event_flag_source version of the event_flag_source signal.
This signal also asserts the external IRQ. When an interrupt enable
bit is set low, the event flag bit reflects the current status of the
event_flag_source signal, and the event flag has no effect on the
external IRQ.
The latched version of an event flag (the interupt_source signal)
can be cleared in two ways. The recommended way is by writing 1
to the corresponding event flag bit. A hardware or software reset
also clears the interupt_source.
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Those events
that require host action should be enabled so that the host is
notified when they occur. For events requiring host intervention,
upon IRQ activation, run the following routine to clear an
interrupt request:
Read the status of the event flag bits that are being
monitored.
Set the interupt enable bit low so that the unlatched
event_flag_source can be monitored directly.
Perform any actions that may be required to quiet the
event_source_flag. In many cases, no specific actions may
be required.
Read the event flag to verify that the actions taken have
quieted the event_flag_source.
Clear the interrupt by writing 1 to the event flag bit.
Set the interrupt enable bits of the events to be monitored.
Noted that some of the event_flag_source signals are latched
signals. These are cleared by writing to the corresponding event
flag bit. Details of each of the event flags can be found in Table 12.
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
DEVICE_RESET
EVENT_FLAG
INTERRUPT
SOURCE
1
0
OTHER
INTERRUPT
SOURCES
IRQ
WRITE_1_TO_EVENT_FLAG
08910-
088
Figure 91. Simplified Schematic of IRQ Circuitry
相关PDF资料 |
PDF描述 |
|---|---|
| UPB2G181MRD6 | CAP ALUM 180UF 400V 20% RADIAL |
| VE-B64-EY | CONVERTER MOD DC/DC 48V 50W |
| AD9148-M5372-EBZ | BOARD EVAL FOR AD9149, ADL5372 |
| AD9737A-EBZ | BOARD EVAL FOR AD9737A |
| MIC2026-1YM | IC DISTRIBUTION SW DUAL 8-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9152BCPZ | 功能描述:16 Bit Digital to Analog Converter 2 56-LFCSP-WQ (8x8) 制造商:analog devices inc. 系列:TxDAC+? 包装:托盘 零件状态:有效 位数:16 数模转换器数:2 建立时间:- 输出类型:Current - Unbuffered 差分输出:是 数据接口:JESD204B 参考类型:内部 电压 - 电源，模拟:3.13 V ~ 3.47 V 电压 - 电源，数字:1.14 V ~ 1.26 V INL/DNL（LSB）:±10，±5 架构:电流源 工作温度:-40°C ~ 85°C 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:1 |
| AD9152BCPZRL | 功能描述:16 Bit Digital to Analog Converter 2 56-LFCSP-WQ (8x8) 制造商:analog devices inc. 系列:TxDAC+? 包装:带卷（TR） 零件状态:有效 位数:16 数模转换器数:2 建立时间:- 输出类型:Current - Unbuffered 差分输出:是 数据接口:JESD204B 参考类型:内部 电压 - 电源，模拟:3.13 V ~ 3.47 V 电压 - 电源，数字:1.14 V ~ 1.26 V INL/DNL（LSB）:±10，±5 架构:电流源 工作温度:-40°C ~ 85°C 封装/外壳:56-WFQFN 裸焊盘，CSP 供应商器件封装:56-LFCSP-WQ（8x8） 标准包装:2,500 |
| AD9152-EBZ | 功能描述:AD9152 TxDAC+? Series 16 Bit 2.25G Samples Per Second Digital to Analog Converter (DAC) Evaluation Board 制造商:analog devices inc. 系列:TxDAC+? 零件状态:有效 DAC 数:2 位数:16 采样率（每秒）:2.25G 数据接口:SPI 建立时间:- DAC 类型:电流 工作温度:-40°C ~ 85°C 所含物品:板，线缆 使用的 IC/零件:AD9152 标准包装:1 |
| AD9152-FMC-EBZ | 功能描述:AD9152 TxDAC+? Series 16 Bit 2.25G Samples Per Second Digital to Analog Converter (DAC) Evaluation Board 制造商:analog devices inc. 系列:TxDAC+? 零件状态:有效 DAC 数:2 位数:16 采样率（每秒）:2.25G 数据接口:SPI 建立时间:- DAC 类型:电流 工作温度:-40°C ~ 85°C 所含物品:板，线缆 使用的 IC/零件:AD9152 标准包装:1 |
| AD9152-M6720-EBZ | 功能描述:AD9152 TxDAC+? Series 16 Bit 2.25G Samples Per Second Digital to Analog Converter (DAC) Evaluation Board 制造商:analog devices inc. 系列:TxDAC+? 零件状态:有效 DAC 数:2 位数:16 采样率（每秒）:2.25G 数据接口:SPI 建立时间:- DAC 类型:电流 工作温度:-40°C ~ 85°C 所含物品:板 使用的 IC/零件:AD9152 标准包装:1 |
发布紧急采购，3分钟左右您将得到回复。