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参数资料
| 型号： | AD9222ABCPZRL7-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/60页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 65MSPS 64LFCSP |
| 标准包装： | 750 |
| 位数： | 12 |
| 采样率（每秒）： | 65M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 950.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 16 个单端，单极；8 个差分，单极 |
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Data Sheet
AD9222
Rev. F | Page 23 of 60
For best dynamic performance, the source impedances driving
VIN + x and VIN x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9222, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9222 either actively or
passively; however, optimum performance is achieved by
driving the analog input differentially. For example, using the
excellent performance and a flexible interface to the ADC (see
Figure 62) for baseband applications. This configuration is
commonly used for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 59 and Figure 60) because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9222.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
CDIFF1
C
1CDIFF IS OPTIONAL.
49.9Ω
0.1μF
1kΩ
AGND
AVDD
ADT1–1WT
1:1 Z RATIO
VIN – x
ADC
AD9222
VIN + x
C
05967-
046
Figure 59. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9222
2V p-p
2.2pF
1k
0.1μF
1kΩ
AVDD
ADT1–1WT
1:1 Z RATIO
16nH
0.1μF
16nH
33
33
499
65
VIN + x
VIN – x
05967-
047
Figure 60. Differential Transformer-Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s
VIN + x pin while the VIN x pin is terminated. Figure 61 details
a typical single-ended input configuration.
2V p-p
R
49.9Ω
0.1F
AVDD
1kΩ 25Ω
1kΩ
AVDD
VIN – x
ADC
AD9222
VIN + x
CDIFF1
C
1CDIFF IS OPTIONAL.
C
05967-
048
Figure 61. Single-Ended Input Configuration
05967-
049
AD8334
1.0kΩ
374Ω
187Ω
R
C
0.1μF
187Ω
0.1μF
10μF
0.1μF
1V p-p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274Ω
VIN – x
ADC
AD9222
VIN + x
1kΩ
AVDD
Figure 62. Differential Input Configuration Using the AD8334
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