参数资料
型号: AD9241ASZ
厂商: Analog Devices Inc
文件页数: 20/24页
文件大小: 0K
描述: IC ADC 14BIT 1.25MSPS 44-MQFP
标准包装: 1
位数: 14
采样率(每秒): 1.25M
数据接口: 并联
转换器数目: 7
功率耗散(最大): 85mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-QFP
供应商设备封装: 44-MQFP(10x10)
包装: 托盘
输入数目和类型: 2 个单端,单极;1 个差分,单极
产品目录页面: 780 (CN2011-ZH PDF)
AD9241
REV. 0
–5–
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25
°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale,
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal; this
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
PIN FUNCTION DESCRIPTIONS
Pin
Number
Name
Description
1
DVSS
Digital Ground
2, 29
AVSS
Analog Ground
3
DVDD
+5 V Digital Supply
4, 28
AVDD
+5 V Analog Supply
5
DRVSS
Digital Output Driver Ground
6
DRVDD
Digital Output Driver Supply
7
CLK
Clock Input Pin
8–10
NC
No Connect
11
BIT 14
Least Significant Data Bit (LSB)
12–23
BIT 13–BIT 2
Data Output Bits
24
BIT 1
Most Significant Data Bit (MSB)
25
OTR
Out of Range
26, 27, 30
NC
No Connect
31
SENSE
Reference Select
32
VREF
Reference I/O
33
REFCOM
Reference Common
34, 35, 38
NC
No Connect
40, 43, 44
36
CAPB
Noise Reduction Pin
37
CAPT
Noise Reduction Pin
39
CML
Common-Mode Level (Midsupply)
41
VINA
Analog Input Pin (+)
42
VINB
Analog Input Pin (–)
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions, and the ideal differ-
ence between first and last code transitions.
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
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