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参数资料
| 型号： | AD9286BCPZ-500 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 48LFSCP |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 330mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，双极 |
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Data Sheet
AD9286
Rev. B | Page 17 of 28
In this mode, the AD9286 can also function as a dual 8-bit,
250 MSPS converter. This may be useful in applications where
both a single 8-bit, 500 MSPS and a dual 8-bit, 250 MSPS converter
are needed. The clock management block requires that CLK±
and AUXCLK± be either 0° or 180°, relative to each other. If
this requirement is satisfied, the circuit correctly time aligns the
data coming out of each ADC core.
If the user desires to operate the AD9286 as a dual 8-bit, 250 MSPS
converter and supply only a single clock, this is achieved by
setting sample mode to simultaneous, with the AUXCLKEN
pin tied to AGND. In this mode, the two ADC cores sample
simultaneously. For a summary of all supported clocking modes,
The AD9286 supports the clocking of each internal ADC with
separate clocks. By setting AUXCLKEN to DRVDD, the user
can supply a differential auxiliary clock to AUXCLK+ and
AUXCLK. In this mode, each internal ADC core has a maximum
sample rate of 250 MSPS. This mode bypasses the internal timing
adjustment blocks.
Interleave Performance
The AD9286 achieves 500 MSPS conversion by time interleaving
two 250 MSPS ADC channels. Although this technique is sufficient
in achieving 8-bit performance, quantifiable errors are introduced.
These errors come from three sources: gain mismatch, imperfect
out-of-phase sampling, and offset mismatch between the two
channels. Distortion appears spectrally in two distinct ways: gain
and timing mismatch appear as an alias spur (see Equation 1), and
offset mismatch appears as a spur located at the Nyquist rate of the
converter (see Equation 2).
fALIAS_SPUR = fS/2 fIN
(1)
where:
fS is the interleaved sample rate.
fIN is the analog input frequency.
fOFFSET_SPUR = fS/2
(2)
where fS is the interleaved sample rate.
The magnitude of the alias spur (AS) contributed by a gain error
is shown in Equation 3.
ASGAIN (dBc) = 20 × log(ASGAIN) = 20 × log(GE/2)
(3)
where:
GE = Gain_Error_Ratio = 1 VFS1/VFS2.
VFSn is the full-scale voltage of Core n.
85
80
75
70
65
60
55
50
45
0
0.5
0.4
0.3
0.2
0.1
AL
IAS
S
P
UR
(
d
Bc)
GAIN MISMATCH (% FS)
09338-
032
Figure 30. ASGAIN as a Function of Gain Mismatch
The magnitude of the alias spur (AS) contributed by a timing
error is shown in Equation 4.
ASTIMING (dBc) = 20 × log(ASTIMING) = 20 × log(θEP/2)
(4)
where θEP = ωA × tE(Radians), with ωA as the analog input
frequency and tE as the clock skew error.
85
80
75
70
65
60
55
50
45
0
12
10
8
6
4
2
AL
IAS
S
P
UR
(
d
Bc)
TIMING ERROR (ps)
09338-
033
Figure 31. ASTIMING as a Function of Timing Error
The total magnitude of the alias spur (AS) is shown in Equation 5.
ASTOTAL (dB) = 20 × log√((ASGAIN)2 + (ASTIMING)2)
(5)
Table 9. Supported Clocking Modes
Effective Number
of Channels
Maximum CLK
Frequency
AUXCLK
Frequency
AUXCLK Phase
Relative to CLK
AUXCLKEN
SPI Register,
Address 0x09, Bit 3
Clock Timing Adjust
One
500 MSPS
N/A
Low
0
Internal
Two
250 MSPS
N/A
Low
1
N/A
Two
250 MSPS
CLK
0°
High
1
N/A
One
250 MSPS
CLK
180°
High
1
External
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