参数资料
型号: AD9548/PCBZ
厂商: Analog Devices Inc
文件页数: 10/112页
文件大小: 0K
描述: BOARD EVAL FOR AD9548
产品变化通告: AD9548 Mask Change 20/Oct/2010
设计资源: AD9548 Schematic
AD9548 BOM
AD9548 Eval Brd Layers
标准包装: 1
主要目的: 计时,时钟发生器
嵌入式:
已用 IC / 零件: AD9548
主要属性: 62.5 ~ 450 MHz 输出频率
次要属性: SPI 和 I2C 兼容控制端口
已供物品:
Data Sheet
AD9548
Rev. E | Page 107 of 112
POWER SUPPLY PARTITIONS
The AD9548 features multiple power supplies, and their power
consumption varies with the AD9548 configuration. This
section provides information about which power supplies can
be grouped together and how the power consumption of each
block varies with frequency.
The numbers quoted here are for comparison only. Please refer
to the Specifications section for exact numbers. With each group,
bypass capacitors of 1 μF in parallel with 10 μF should be used.
Upon applying power to the device, internal circuitry monitors
the 1.8 V digital core supply and the 3.3 V digital I/O supply.
When these supplies cross the desired threshold level, the device
generates an internal 10 μs reset pulse. This pulse does not
appear on the RESET pin.
3.3 V SUPPLIES
The 3.3 V supply domain consists of two main partitions, digital
(DVDD3) and analog (AVDD3). Take care to keep these two
supply domains separate.
Furthermore, the AVDD3 consists of two subdomains: the clock
distribution output domain (Pin 31, Pin 37, Pin 38, and Pin 44)
and the rest of the AVDD3 supply connections. Generally, these
supply domains can be joined together. However, if an application
requires 1.8 V CMOS driver operation in the clock distribution
output block, then provide one 1.8 V supply domain to power
the clock distribution output block. Each output driver has a
dedicated supply pin, as shown in Table 155.
Table 155. Output Driver Supply Pins
Output Driver
Supply Pin
OUT0
31
OUT1
37
OUT2
38
OUT3
44
1.8 V SUPPLIES
The 1.8 V supply domain consists of two main partitions, digital
(DVDD) and analog (AVDD). These two supply domains must
be kept separate.
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