- 您现在的位置：买卖IC网 > PDF目录16835 > AD9548/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9548 PDF资料下载
参数资料
| 型号： | AD9548/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/112页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 产品变化通告： | AD9548 Mask Change 20/Oct/2010 |
| 设计资源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要属性： | 62.5 ~ 450 MHz 输出频率 |
| 次要属性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页
Data Sheet
AD9548
Rev. E | Page 109 of 112
CALCULATING DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients (, , , and (see Figure 41))
relate to the time constants (T1, T2, and T3) associated with the
equivalent analog circuit for a third order loop filter (see Figure 68).
Note that AD9548 evaluation software contains a profile
designer that will compute these coefficients for you. The
user should not normally need to use these formulas.
R2
FROM
CHARGE
PUMP
TO
VCO
R3
C3
C1
C2
0
802
2-
0
42
Figure 68. Third Order Analog Loop Filter
The design process begins by deciding on two design
parameters related to the second order loop filter shown in
margin (.
R2
FROM
CHARGE
PUMP
TO
VCO
C1
C2
08
02
2
-04
3
Figure 69. Second Order Analog Loop Filter
An analysis of the second order loop filter leads to its primary
time constant, T1. It can be shown that T1 is expressible in terms
of fP and as
)
cos(
)
sin(
1
P
1
T
where
P
f
2
.
An analysis of the third order loop filter leads to the definition
of another time constant, T3. It can be shown that T3 is
expressible in terms of the desired amount of additional
attenuation introduced by R3 and C3 at some specified
frequency offset (fOFFSET) from the PLL output frequency.
OFFSET
ATTEN
3
T
1
10 10
where
OFFSET
f
2
.
Note that ATTEN is the desired excess attenuation in decibels.
Furthermore, ATTEN and ωOFFSET should be chosen so that
P
f
T
5
1
3
With an expression for T1 and T3, it is possible to define an
adjusted open-loop bandwidth (fC) that is slightly less than fP. It
can be shown that ωC (fC expressed as a radian frequency) is
expressible in terms of T1, T3, and θ (phase margin) as
1
)
tan(
1
)
tan(
2
3
1
3
1
3
1
3
1
3
1
3
1
C
T
It can also be shown that the adjusted open-loop bandwidth
leads to T2 (the secondary time constant of the second order
loop filter) expressed as
3
1
C
2
T
2
1
Calculation of the digital loop filter coefficients requires a
scaling constant, K (related to the system clock frequency, fS),
and the PLL feedback divide ratio, D.
S
f
K
33
2
125
,
578
,
517
,
30
1
V
U
S
D
where S, U, and V are the integer and fractional feedback
divider values that reside in the profile registers. Keep in mind
that the desired integer feedback divide ratio is one more than
the stored value of S (hence, the +1 term in the equation for D
in this equation). This leads to the digital filter coefficients
given by
2
2
1
2
C
3
C
1
C
1
2
C
T
K
T
D
T
2
1
S
T
f
1
32
1
S T
f
32
3
S T
f
32
Calculation of the coefficient register values requires the
application of some special functions described as follows:
The if() function
y = if(test_statement, true_value, false_value)
where test_statement is a conditional expression (for example, x
< 3), true_value is what y equals if the conditional expression is
true, and false_value is what y equals if the conditional
expression is false.
The round() function
y = round(x)
相关PDF资料 |
PDF描述 |
|---|---|
| SFSD-15-28-H-10.00-DR-NUX | CABLE ASSY SOCKET 30POS 28AWG |
| H3AAH-2436G | IDC CABLE - HSC24H/AE24G/HSC24H |
| EEU-FR1H181LB | CAP ALUM 180UF 50V 20% RADIAL |
| MAX6174AASA+ | IC VREF SERIES PREC 4.096V 8SOIC |
| GBC13DRXS-S734 | CONN EDGECARD 26POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9549ABCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
发布紧急采购，3分钟左右您将得到回复。