参数资料
| 型号： | AD9577BCPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/44页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR 40LFCSP |
| 标准包装： | 750 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 扇出缓冲器（分配），网络时钟发生器 |
| PLL： | 是 |
| 主要目的： | 以太网，PCI Express（PCIe），SONET/SDH |
| 输入： | 时钟，晶体 |
| 输出： | LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 637.5MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | AD9577BCPZ-R7TR |
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Data Sheet
AD9577
Rev. 0 | Page 25 of 44
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for each
cycle. Actual signals, however, display a certain amount of
variation from ideal phase progression over time, which is
called phase jitter. Although many causes can contribute
to phase jitter, one major cause is random noise, which is
characterized statistically as being Gaussian (normal) in
distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz band-
width with respect to the power at the carrier frequency. For each
measurement, the offset from the carrier frequency is also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 12 kHz to
20 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Time Jitter
Phase noise is a frequency domain phenomenon. In the
time domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
vary. In a square wave, the time jitter is seen as a displacement
of the edges from their ideal (regular) times of occurrence. In
both cases, the variations in timing from the ideal are the time
jitter. Because these variations are random in nature, the time
jitter is specified in units of seconds root mean square (rms) or
1 sigma of the Gaussian distribution.
Additive Phase Noise
It is the amount of phase noise that is attributable to the device
or subsystem being measured. The phase noise of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device affects the
total system phase noise when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own phase noise to the total. In many cases, the phase noise
of one element dominates the system phase noise.
Additive Time Jitter
It is the amount of time jitter that is attributable to the device
or subsystem being measured. The time jitter of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device will affect the
total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
Random Jitter Measurement
On the AD9577, the rms jitter measurements are made by
integrating the phase noise, with spurs disabled. There are two
reasons for this. First, because the part is highly configurable, any
measured spurs are a function of the current programmed state
of the device. For example, there may be a small reference spur at
the PFD frequency present on the output spectrum. If the PFD
operates at 19.44 MHz (which is common for telecommunications
applications), the resulting jitter falls within the normal 12 kHz
to 20 MHz integration bandwidth. When the PFD operates
above 20 MHz, the deterministic jitter is not included in the
measurement. As another example, for PLL2, the value of the
chosen FRAC and MOD values affects the amplitude and
location of a spur, and therefore, it is not possible to configure
the PLL to provide a general measurement that includes spurs.
The second, and more significant reason, is due to the statistical
nature of spurious components. The jitter performance information
of the clock generator is required so that a jitter budget for the
complete communications channel can be established. By
knowing the jitter characteristics at the ultimate receiver, the
data bit error rate (BER) can be estimated to ensure robust data
transfer. The received jitter characteristic consists of random
jitter (RJ), due to random perturbations such as thermal noise,
and deterministic jitter (DJ), due to deterministic perturbations
such as crosstalk spurs. To make an estimate of the BER, the
total jitter peak-to-peak (TJ p-p) value must be known. It is the
total jitter value that determines the amount of eye closure at
the receiver and, consequently, the bit error rate. The TJ p-p
value is specified for a given number of clock edges. For
example, in networking applications, the TJ is specified for 112
clock edges. The equation for the total jitter peak-to-peak is
TJ p-p = DJ p-p + 2 × Q × RJ rms
(1)
where the Q factor represents the ratio of the expected peak
deviation to the standard deviation in a Gaussian process for a
given population (of edge crossings). For 112 clock edges, Q is
7.03; therefore, for networking applications, the total jitter peak-
to-peak is estimated by
TJ p-p = DJ p-p + 14.06 × RJ rms
(2)
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