参数资料
型号: AD9600ABCPZ-125
厂商: Analog Devices Inc
文件页数: 2/72页
文件大小: 0K
描述: IC ADC 10BIT 125MSPS 64LFCSP
标准包装: 1
位数: 10
采样率(每秒): 125M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 800mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 托盘
输入数目和类型: 4 个单端,单极;2 个差分,单极
AD9600
Rev. B | Page 10 of 72
TIMING CHARACTERISTICS
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
Setup time between SYNC and the rising edge of CLK+
0.24
ns
tHSYNC
Hold time between SYNC and the rising edge of CLK+
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
10
ns
SPORT TIMING REQUIREMENTS
tCSSCLK
Delay from the rising edge of CLK+ to the rising edge of SMI SCLK
3.2
4.5
6.2
ns
tSSCLKSDO
Delay from the rising edge of SMI SCLK to SMI SDO
0.4
0
0.4
ns
tSSCLKSDFS
Delay from the rising edge of SMI SCLK to SMI SDFS
0.4
0
0.4
ns
TIMING DIAGRAMS
06
90
9-
01
2
CLK+
DCOA/DCOB
CH A/CH B DATA
N
N+ 1
N+ 2
N+ 3
N+ 4
N+ 5
N+ 6
N+ 7
N+ 8
N – 12
N – 11
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 13
CLK–
tCLK
tPD
tS
tH
tDCO
tCLK
tA
CH A/CH B FAST
DETECT
N – 1
N + 2
N + 3
N + 4
N + 5
N + 6
N – 3
N – 2
N – 10
N + 1
N
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing
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