- 您现在的位置：买卖IC网 > PDF目录10527 > AD9600ABCPZ-125 (Analog Devices Inc)IC ADC 10BIT 125MSPS 64LFCSP PDF资料下载
参数资料
| 型号： | AD9600ABCPZ-125 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/72页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 125MSPS 64LFCSP |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 125M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 800mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
AD9600
Rev. B | Page 40 of 72
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map registers table (Table 22) has eight
bit locations. The memory map is divided into four sections: the
chip configuration registers (Address 0x00 to Address 0x02), the
channel index and transfer registers (Address 0x05 and Address
0xFF), the ADC functions registers (Address 0x08 to Address
0x25), and the digital feature control registers (Address 0x100 to
Address 0x11B).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a default value of 0xC0, meaning that
Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the
default reference selection setting. The default value uses a 2.0 V
peak-to-peak reference. For more information on this function and
others, see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This application note details the functions controlled
by Register 0x00 to Register 0xFF. The remaining registers
(from Register 0x100 to Register 0x11B) are documented in
the Memory Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 22
are currently not supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
When the AD9600 comes out of a reset, critical registers are
loaded with default values. The default values for the registers
are given in the memory map registers table (Table 22).
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit (Bit 0 of Register 0xFF) is set. The
internal update takes place when the transfer bit is set, and the
bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be individually programmed for each channel.
In these cases, channel address locations are internally
duplicated for each channel. These registers are designated as
local registers in Table 22 and can be accessed by setting the
appropriate Channel A or Channel B bits in Register 0x05. If
both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are
set during an SPI read cycle, the part returns the value for
Channel A.
On the other hand, registers that are designated as global registers
in Table 22 affect the entire part or the channel features for which
independent settings are not allowed between the channels. The
settings in Register 0x05 do not affect the global registers.
相关PDF资料 |
PDF描述 |
|---|---|
| ICL3237CAZ | IC 5DRVR/3RCVR RS232 3V 28-SSOP |
| AMIS42665TJAA1G | TRANSCEIVER CAN HS LP 8-SOIC |
| VE-J6W-MY-F2 | CONVERTER MOD DC/DC 5.5V 50W |
| ICL3243ECAZ | IC 3DRVR/5RCVR RS232 3V 28-SSOP |
| AD9054ABSTZ-135 | IC ADC 8BIT 135MSPS 44-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9600ABCPZ-150 | 功能描述:IC ADC 10BIT 150MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9600BCPZ-105 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-125 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 125Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-150 | 制造商:Analog Devices 功能描述: |
| AD9601 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter |
发布紧急采购，3分钟左右您将得到回复。