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参数资料
| 型号： | AD9608BCPZ-105 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 10BIT 64-LFCSP |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 105M |
| 数据接口： | LVDS，并联，串行，SPI |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个单端，2 个差分 |
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AD9608
Rev. 0 | Page 27 of 40
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
100
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0997
7-
06
1
Figure 55. Differential PECL Sample Clock (Up to 1 GHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 56. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
09977-
062
Figure 56. Differential LVDS Sample Clock (Up to 1 GHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
09
977
-063
Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9608 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9608 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow
the clock divider to be resynchronized on every SYNC signal
or only on the first SYNC signal after the register is written.
A valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. A ±5% tolerance is commonly
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9608 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9608. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 58.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
40
45
50
55
60
65
70
35
40
45
50
55
60
65
S
NR
(
d
BF
s)
POSITIVE DUTY CYCLE (%)
DCS ON
DCS OFF
09977
-036
Figure 58. SNR vs. DCS On/Off
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