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| 型号： | AD9752-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/23页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9752 |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 设置时间： | 35ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9752 |
REV. 0
AD9752
–18–
AD9752
(“I DAC”)
AD9752
(“Q DAC”)
IOUTA
IOUTB
QOUTA
QOUTB
DCOM
FSADJ
REFIO
SLEEP
RSET2
1.9k
0.1 F
CLK
Q DATA
INPUT
I DATA
INPUT
DVDD
AVDD
100W
500
100
CFILTER
100
500
634
+3V
IIPP
IIPN
IIQP
IIQN
AD6122
REFLO
ACOM
REFLO
AVDD
REFIO
FSADJ
RSET1
2k
RCAL
220
U1
U2
AVDD
LATCHES
500
DAC
LATCHES
100
PHASE
SPLITTER
2
TEMPERATURE
COMPENSATION
GAIN
CONTROL
SCALE
FACTOR
REFIN
VGAIN
GAIN
CONTROL
LOIPP
LOIPN
TXOPP
TXOPN
VCC
Figure 38. CDMA Transmit Application Using AD9752
Figure 39 shows the AD9752 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the given
test vector is measured at 70 dB.
–20
–80
–120
CENTER 16.384MHz
SPAN 14.096MHz
1.4096MHz
–30
–70
–90
–110
–50
–60
–100
–40
CO
CL1
CU1
Figure 39. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dBm
It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this imple-
mentation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 40 shows a block diagram of
such an implementation using the AD9752.
50
AD9752
LPF
50
TO
MIXER
STEL-1130
QAM
12
COS
12
SIN
12
I DATA
Q DATA
12
CARRIER
FREQUENCY
12
STEL-1177
NCO
CLOCK
Figure 40. Digital QAM Architecture
AD9752 EVALUATION BOARD
General Description
The AD9752-EB is an evaluation board for the AD9752 12-bit
D/A converter. Careful attention to layout and circuit design
combined with a prototyping area allow the user to easily and
effectively evaluate the AD9752 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9752
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators, with the
on-board option to add a resistor network for proper load
termination. Provisions are also made to operate the AD9752
with either the internal or external reference, or to exercise the
power-down feature.
Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9752 evaluation board.
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