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参数资料
| 型号： | AD9752-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/23页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9752 |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 设置时间： | 35ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9752 |
REV. 0
AD9752
–9–
FUNCTIONAL DESCRIPTION
Figure 17 shows a simplified block diagram of the AD9752.
The AD9752 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9752 have separate
power supply inputs (i.e., AVDD and DVDD). The digital
section, which is capable of operating up to a 125 MSPS clock
rate and over a +2.7 V to +5.5 V operating range, consists of
edge-triggered latches and segment decoding logic circuitry.
The analog section, which can operate over a +4.5 V to +5.5 V
range, includes the PMOS current sources, the associated differ-
ential switches, a 1.20 V bandgap voltage reference and a refer-
ence control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference VREFIO,
sets the reference current IREF, which is mirrored over to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is thirty-two times the value of IREF.
DAC TRANSFER FUNCTION
The AD9752 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 4095) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function
of both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/4096)
× I
OUTFS
(1)
IOUTB = (4095 – DAC CODE)/4096
× I
OUTFS
(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 × IREF
(3)
where IREF = VREFIO/RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50
or 75 cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 4095)/4096} ×
(32 RLOAD/RSET) × VREFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9752 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9752
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
DIGITAL DATA INPUTS (DB11–DB0)
150pF
+1.20V REF
AVDD
ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB11–DB3
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
RSET
2k
0.1 F
IOUTA
IOUTB
0.1 F
AD9752
SLEEP
LATCHES
IREF
VREFIO
CLOCK
IOUTB
IOUTA
RLOAD
50
VOUTB
VOUTA
RLOAD
50
VDIFF = VOUTA – VOUTB
Figure 17. Functional Block Diagram
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