收藏本站
参数资料
型号： AD9778A-DPG2-EBZ
厂商： Analog Devices Inc
文件页数： 22/56页
文件大小： 0K
描述： BOARD EVALUATION FOR AD9778A
标准包装： 1
系列： *
DAC 的数量： 2
位数： 14
采样率（每秒）： 1G
数据接口： 并联
DAC 型： 电流
工作温度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9778A
AD9776A/AD9778A/AD9779A
Rev. B | Page 29 of 56
Table 14. 3-Wire Interface Register Description
Register
Address
Bits
Register Name
Parameter
Function
Default
Comm
0x00
7
SDIO bidirectional
0: use SDIO pin as input data only.
1: use SDIO as both input and output data.
0
0x00
6
LSB/MSB first
0: first bit of serial data is MSB of data byte.
1: first bit of serial data is LSB of data byte.
0
0x00
5
Software reset
Bit must be written with a 1 and then 0 to soft reset
the 3-wire interface register map.
0
0x00
4
Power-down mode
0: all circuitry is active.
1: disable all digital and analog circuitry, only
3-wire interface port is active.
0x00
3
Auto power-down enable
Controls auto power-down mode. See the Power-
Down and Sleep Modes section.
0
0x00
1
PLL lock indicator
(read only)
0: PLL is not locked.
1: PLL is locked.
Digital Control
0x01
7:6
Interpolation Factor[1:0]
00: 1× interpolation.
01: 2× interpolation.
10: 4× interpolation.
11: 8× interpolation.
00
0x01
5:2
Filter Modulation Mode[3:0]
See Table 19 for filter modes.
0000
0x01
1
DATACLK Delay[4]
Sets MSB of delay of REFCLK input to DATACLK
output.
0
0x01
0
Zero stuffing enable
0: zero stuffing off.
1: zero stuffing on.
0
0x02
7
Data format
0: twos compliment.
1: unsigned binary.
0
0x02
6
Single port
0: both P1D and P2D data ports enabled.
1: data for both DACs received on P1D data port.
0
0x02
5
Real mode
0: enable Q path for signal processing.
1: disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled).
0
0x02
4
DATACLK delay enable
Enables the DATACLK delay feature. More details
on this feature are shown in the Optimizing the
Data Input Timing section.
0x02
3
Inverse sinc enable
0: inverse sinc filter disabled.
1: inverse sinc filter enabled.
0
0x02
2
DATACLK invert
0: output DATACLK same phase as internal data
sampling clock, DCLK_SMP signal.
1: output DATACLK opposite phase as internal data
sampling clock, DCLK_SMP signal.
0
0x02
1
TxEnable invert
Inverts the polarity of Pin 39, the TXENABLE input
pin (also functions as IQSELECT).
0
0x02
0
Q first
0: in interleaved mode, the I data precedes the
Q data on the input port.
1: in interleaved mode, the Q data precedes the
I data on the input port.
相关PDF资料
PDF描述
SDR0403-101KL INDUCTOR 100UH 10% NON-SHLD SMD
AD9776A-DPG2-EBZ BOARD EVALUATION FOR AD9776A
DC1009A-B BOARD DELTA SIGMA ADC LTC2488
AD9787-DPG2-EBZ BOARD EVALUATION FOR AD9787
ESA10DTKS CONN EDGECARD 20POS DIP .125 SLD
相关代理商/技术参数
参数描述
AD9778A-EBZ 制造商:Analog Devices 功能描述:Dual 12 /14 /16 Bit, 1 GSPS, Digital To Analog Converters Development Kit 制造商:Analog Devices 功能描述:DUAL 14B, 1.0 GSPS TXDAC - Bulk
AD9778BSVZ 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:*
AD9778BSVZ1 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters
AD9778BSVZRL 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k
AD9778BSVZRL1 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*