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参数资料
| 型号： | AD9778A-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9778A |
| 标准包装： | 1 |
| 系列： | * |
| DAC 的数量： | 2 |
| 位数： | 14 |
| 采样率（每秒）： | 1G |
| 数据接口： | 并联 |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9778A |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 50 of 56
SYNCHRONIZING DEVICES TO A SYSTEM CLOCK
The AD9776A/AD9778A/AD9779A offer a pulse mode synchro-
nization scheme (see Figure 89) to align the DAC outputs of
multiple devices within a system to the same DACCLK edge.
The internal clocks are synchronized by providing either a one-
time pulse or a periodic signal to the SYNC_I inputs (SYNC_I+,
SYNC_I). The SYNC_I signal is sampled by the internal
DACCLK sample rate clock.
The SYNC_I input frequency has the following constraint:
fSYNC_I ≤ fDATA
When the internal clocks are synchronized, the data-sampling
clocks between all devices are phase aligned. The data input
timing relationships can be referenced to either REFCLK or
DATACLK.
For this synchronization scheme, all devices are slave devices,
and the system clock generation/distribution chip serves as the
master. It is vital that the SYNC_I signal be distributed between
the DACs with low skew. Likewise, the REFCLK signals must be
distributed with low skew. Any skew on these signals between the
DACs must be accounted for in the timing budget. Figure 89
shows an example clock and synchronization input scheme.
Figure 90 shows the timing of the SYNC_I input with respect to
the REFCLK input. Note that although the timing is relative to
the REFCLK signal, SYNC_I is sampled at the DACCLK rate.
This means that the rising edge of the SYNC_I signal must occur
after the hold time of the preceding DACCLK rising edge, not
the preceding REFCLK rising edge.
INTERRUPT REQUEST OPERATION
The IRQ pin (Pin 71) acts as an alert in the event that the
device has a timing error and should be queried (by reading
Register 0x19) to determine the exact fault condition. The IRQ pin
is an open-drain, active low output. The IRQ pin should be pulled
high external to the device. This pin can be tied to the IRQ pins
of other devices with open-drain outputs to wire-OR these pins
together.
There are two different error flags that can trigger an interrupt
request: a data timing error flag or a sync timing error flag. By
default, when either or both of these error flags are set, the IRQ pin
is active low. Either or both of these error flags can be masked
to prevent them from activating an interrupt on the IRQ pin.
The error flags are latched and remain active until the interrupt
register, Register 0x19, is either read from or the error flag bits
are overwritten.
SYSTEM CLOCK
LOW SKEW
CLOCK DRIVER
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
REFCLK
SYNC_I
REFCLK
SYNC_I
OUT
MATCHED
LENGTH TRACES
PULSE
GENERATOR
06
45
2-
31
1
Figure 89. Multichip Synchronization in Pulse Mode
DACCLK
REFCLK
SYNC_I
tS_SYNC
tH_SYNC
06
45
2-
31
2
Figure 90. Timing Diagram of SYNC_I with Respect to REFCLK When Synchronizing Multiple Devices to Each Other
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9778A-EBZ | 制造商:Analog Devices 功能描述:Dual 12 /14 /16 Bit, 1 GSPS, Digital To Analog Converters Development Kit 制造商:Analog Devices 功能描述:DUAL 14B, 1.0 GSPS TXDAC - Bulk |
| AD9778BSVZ | 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9778BSVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
| AD9778BSVZRL | 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9778BSVZRL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
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