参数资料
| 型号： | AD9779ABSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 53/56页 |
| 文件大小： | 0K |
| 描述： | DAC 16BIT 1.0GSPS 100-TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 设计资源： | Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021) |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 300mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 1G |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 6 of 56
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
2.0
V
Input VIN Logic Low
0.8
V
Maximum Input Data Rate at Interpolation
1×
300
MSPS
2×
250
MSPS
4×
200
MSPS
8×
DVDD18, CVDD18 = 1.8 V ± 5%
112.5
MSPS
DVDD18, CVDD18 = 1.9 V ± 5%
125
MSPS
DVDD18, CVDD18 = 2.0 V ± 2%
137.5
MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High
2.4
V
Output VOUT Logic Low
0.4
V
DATACLK Output Duty Cycle
At 250 MHz, into 5 pF load
40
50
60
%
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I)
SYNC_I+ = VIA, SYNC_I = VIB
Input Voltage Range, VIA or VIB
825
1575
mV
Input Differential Threshold, VIDTH
100
+100
mV
Input Differential Hysteresis, VIDTHH VIDTHL
20
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
LVDS Input Rate
Additional limits on fSYNC_I apply; see description of
Register 0x05, Bits[3:1], in Table 14
250
MSPS
Setup Time, SYNC_I to REFCLK
0.4
ns
Hold Time, SYNC_I to REFCLK
0.55
ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O)
SYNC_O+ = VOA, SYNC_O = VOB, 100 Ω termination
Output Voltage High, VOA or VOB
1375
mV
Output Voltage Low, VOA or VOB
1025
mV
Output Differential Voltage, |VOD|
150
200
250
mV
Output Offset Voltage, VOS
1150
1250
mV
Output Impedance, RO
Single-ended
80
100
120
Ω
DAC CLOCK INPUT (REFCLK+, REFCLK)
Differential Peak-to-Peak Voltage
400
800
2000
mV
Common-Mode Voltage
300
400
500
mV
Maximum Clock Rate
DVDD18, CVDD18 = 1.8 V ± 5%, PLL off
900
MHz
DVDD18, CVDD18 = 1.9 V ± 5%, PLL off
1000
MHz
DVDD18, CVDD18 = 2.0 V ± 2%, PLL off
1100
MHz
DVDD18, CVDD18 = 2.0 V ± 2%, PLL on
250
MHz
1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
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| AD9779A-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9779A RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9779A-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk |
| AD9779AMOD-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk |
| AD9779AXSVZ | 制造商:Analog Devices 功能描述:DUAL 16-BIT, 1 GSPS, DIGITAL-TO-ANALOG CONVERTER - Bulk |
| AD9779BSV | 制造商:Analog Devices 功能描述:DAC 2CH INTERPOLATION FLTR 16BIT 100TQFP EP - Bulk |
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