- 您现在的位置：买卖IC网 > PDF目录17065 > AD9787-DPG2-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9787 PDF资料下载
参数资料
| 型号： | AD9787-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9787 |
| 标准包装： | 1 |
| 系列： | * |
| DAC 的数量： | 2 |
| 位数： | 14 |
| 采样率（每秒）： | 800M |
| 数据接口： | 串行 |
| 设置时间： | 22ms |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9787 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
AD9785/AD9787/AD9788
Rev. A | Page 27 of 64
The data synchronization control register (DSCR) comprises two bytes located at Address 0x02.
Table 12. Data Synchronization Control Register (DSCR)
Address
Bit
Name
Description
0x02
[15:11]
DATACLK Delay [4:0]
Controls the amount of delay applied to the output data clock signal. The minimum delay
corresponds to the 00000 state, and the maximum delay corresponds to the 11111 state.
The minimum delay is 0.7 ns and the maximum delay is 6.5 ns. The incremental delay is
190 ps and corresponds to an incremental change in the data clock delay bits.
[10:7]
Data Timing Margin [3:0]
The data timing margin bits control the amount of delay applied to the data and clock
signals used for checking setup and hold times, respectively, on the input data ports, with
respect to the internal data assembler clock. The minimum delay corresponds to the 0000
state, and the maximum delay corresponds to the 1111 state. The delays are 190 ps.
[6]
LVDS data clock enable
0: Default. When the LVDS data clock enable bit is cleared, the SYNC_O+ and SYNC_O
LVDS pad cells are driven by the multichip synchronization logic.
1: When the LVDS data clock enable bit is set, the SYNC_O+ and SYNC_O LVDS pad cells
are driven by the signal that drives the CMOS DATACLK output pad.
[5]
DATACLK invert
0: Default. When the data clock invert bit is cleared, the DATACLK signal is in phase with
the clock that samples the data into the part.
1: When the DATACLK invert bit is set, the DATACLK signal is inverted from the clock that
samples the data into the part.
[4]
DATACLK delay enable
0: Default. When the DATACLK delay enable bit is cleared, the data port input
synchronization function is effectively inactive and the delay is bypassed.
1: When the DATACLK delay enable bit is set, the data port input synchronization function
is active and controlled by the data delay mode bits. The data output clock is routed
through the delay cell.
[3]
Data timing mode
Determines the timing optimization mode. See the Optimizing the Data Input Timing
section for details.
0: Manual timing optimization mode
1: Automatic timing optimization mode
[2]
Set high
This bit should always be set high.
[1]
Data sync polarity
0: Default. The digital input data sampling edge is aligned with the falling edge of DCI.
1: The digital input data sampling edge is aligned with the rising edge of DCI.
Used only in slave mode (see the MSCR register, Address 0x03, Bit 16).
[0]
Reserved
Reserved for future use.
相关PDF资料 |
PDF描述 |
|---|---|
| ESA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
| SDR0604-331KL | INDUCTOR POWER 330UH 10% SMD |
| AD9788-DPG2-EBZ | BOARD EVALUATION FOR AD9788 |
| SLPX223M025E7P3 | CAP ALUM 22000UF 25V 20% SNAP |
| EMA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9787-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk |
| AD9788 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO |
| AD9788BSVZ | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD9788BSVZRL | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9788-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9788 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
发布紧急采购，3分钟左右您将得到回复。