- 您现在的位置：买卖IC网 > PDF目录17065 > AD9787-DPG2-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9787 PDF资料下载
参数资料
| 型号： | AD9787-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9787 |
| 标准包装： | 1 |
| 系列： | * |
| DAC 的数量： | 2 |
| 位数： | 14 |
| 采样率（每秒）： | 800M |
| 数据接口： | 串行 |
| 设置时间： | 22ms |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9787 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
AD9785/AD9787/AD9788
Rev. A | Page 46 of 64
Table 33 lists the register settings required to enable the PN
code mode synchronization feature.
Table 33. Register Settings for Enabling PN Code Mode
Register
Bit
Parameter
Value
0x01
[13]
PN code sync enable
1
[12]
Sync mode select
1
[11]
Pulse sync enable
0
0x03
[31:27]
Correlate Threshold
[4:0]
10000
[26]
SYNC_I enable
1
[25]
SYNC_O enable
0 (slave devices)
1 (master device)
[10]
Set high
1
To verify that the devices have successfully synchronized, read
back the sync lock status bit on all devices (Register 0x09,
Bit 10). The sync lock status bit should read back as 1 on all
devices. Next, read back the sync lock lost status bit on all
devices (Register 0x09, Bit 11). The sync lock lost status bit
should read back as 0 on all devices. To clear the sync lock lost
status bit, set the clear lock indicator bit to 1, followed by a 0
(Register 0x09, Bit 12).
Because the SYNC_O signal generated by the master is spread
over many bits, this method of synchronization is very robust.
Any individual bits that may become corrupted or somehow
misread by the slave device usually have no effect on the
synchronization of the device. If the devices do not reliably
synchronize, there are several options for correcting the situation.
The SYNC_O Delay [4:0] value (Register 0x03, Bits [15:11]) on
the master device can be used to adjust the timing in 80 ps steps
effective across all devices. In addition, the SYNC_O polarity bit
(Register 0x03, Bit 9) on the master device can be set to provide
a delay of one half the DACCLK period. The SYNC_I Delay [4:0]
bits (Register 0x03, Bits [23:19]) can be used to adjust the
timing on a single slave device in 80 ps steps.
The Correlate Threshold [4:0] value (Register 0x03,
Bits [31:27]) indicates how closely the code of the received
SYNC_I signal is to the expected code. A high threshold
requires a closer match of the encoded signal to set the
sync lock status bit; a lower value reduces the matching
requirements to set the sync lock status bit.
Increasing the Correlate Threshold [4:0] value makes the part
more resistant to false synchronization locks but requires a
lower bit error rate on the SYNC_I input to maintain locked
status. Decreasing the Correlate Threshold [4:0] value makes
the part more susceptible to false synchronization locks, but
maintains a locked status in the face of a higher bit error rate
on the SYNC_I input (that is, it is more noise resistant). The
recommended value for Correlate Threshold [4:0] is the default
value of 16.
INTERRUPT REQUEST OPERATION
The IRQ pin (Pin 71) acts as an alert that the device has
experienced a timing error and that it should be queried (by
reading Register 0x09) to determine the exact fault condition.
The IRQ pin is an open-drain, active low output. The IRQ pin
should be pulled high external to the device. This pin may be
tied to the IRQ pins of other devices with open-drain outputs to
wire-OR these pins together.
There are two different error flags that can trigger an interrupt
request: a data timing error or a sync timing error. By default,
when either or both of these error flags are set, the IRQ pin is
active low. Either or both of these error flags can be masked to
prevent them from activating an interrupt on the IRQ pin.
The error flags are latched and remain active until the flag bits
are overwritten.
相关PDF资料 |
PDF描述 |
|---|---|
| ESA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
| SDR0604-331KL | INDUCTOR POWER 330UH 10% SMD |
| AD9788-DPG2-EBZ | BOARD EVALUATION FOR AD9788 |
| SLPX223M025E7P3 | CAP ALUM 22000UF 25V 20% SNAP |
| EMA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9787-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk |
| AD9788 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO |
| AD9788BSVZ | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD9788BSVZRL | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9788-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9788 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
发布紧急采购，3分钟左右您将得到回复。