- 您现在的位置：买卖IC网 > PDF目录10979 > AD9910BSVZ (Analog Devices Inc)IC DDS 1GSPS 14BIT PAR 100TQFP PDF资料下载
参数资料
| 型号： | AD9910BSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/64页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
AD9910
Data Sheet
Rev. D | Page 24 of 64
Auxiliary DAC
An 8-bit auxiliary DAC controls the full-scale output current of
the main DAC (IOUT). An 8-bit code word stored in the appropriate
register map location sets IOUT according to the following equation:
+
=
96
1
4
.
86
CODE
R
I
SET
OUT
where RSET is the value of the RSET resistor (in ohms) and CODE
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with RSET = 10,000 Ω and CODE = 127, then IOUT =
20.07 mA.
INVERSE SINC FILTER
The sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated into the AD9910. The
DAC output spectrum is shaped by the characteristic sin(x)/x
(or sinc) envelope, due to the intrinsic zero-order hold effect
associated with DAC generated signals. The sinc envelope
can be compensated for because its shape is well known. This
envelope restoration function is provided by the inverse sinc
filter preceding the DAC. The inverse sinc filter is implemented
as a digital FIR filter. It has a response characteristic that very
nearly matches the inverse of the sinc envelope. The response
of the inverse sinc filter is shown in Figure 28 (with the sinc
envelope for comparison).
The inverse sinc filter is enabled using CFR1[22]. The filter tap
coefficients are given in Table 6. The filter operates by distorting
the data prior to its arrival at the DAC in such a way as to
compensate for the sinc envelope that otherwise distorts the
spectrum.
When the inverse sinc filter is enabled, it introduces a ~3.0 dB
insertion loss. The inverse sinc compensation is effective for output
frequencies up to approximately 40% of the DAC sample rate.
Table 6. Inverse Sinc Filter Tap Coefficients
Tap No.
Tap Value
1, 7
35
2, 6
+134
3, 5
562
4
+6729
In Figure 28, the sinc envelope introduces a frequency dependent
attenuation that can be as much as 4 dB at the Nyquist frequency
( of the DAC sample rate). Without the inverse sinc filter, the
DAC output suffers from the frequency dependent droop of
the sinc envelope. The inverse sinc filter effectively flattens the
droop to within ±0.05 dB, as shown in Figure 29, which shows
the corrected sinc response with the inverse sinc filter enabled.
1
0
–1
–2
–3
–4
0
0.1
0.2
0.4
0.3
0.5
06479-
011
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
INVERSE
SINC
Figure 28. Sinc and Inverse Sinc Responses
–2.8
–2.9
–3.0
–3.1
0
0.1
0.2
0.4
0.3
0.5
06479-
012
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
COMPENSATED RESPONSE
Figure 29. DAC Response with Inverse Sinc Compensation
CLOCK INPUT (REF_CLK/REF_CLK)
REF_CLK/REF_CLK Overview
The AD9910 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/REF_CLK input pins. The REF_CLK input can be
driven directly from a differential or single-ended source, or it
can accept a crystal connected across the two input pins. There
is also an internal phase-locked loop (PLL) multiplier that can
be independently enabled. A block diagram of the REF_CLK
functionality is shown in Figure 30. The various input configu-
rations are controlled by the XTAL_SEL pin and the control bits
in the CFR3 register. Figure 30 also shows how the CFR3 control
bits are associated with specific functional blocks.
相关PDF资料 |
PDF描述 |
|---|---|
| MCF51EM128CLL | IC MCU 32BIT 128KB FLASH 100LQFP |
| AD9957BSVZ | IC DDS 1GSPS 14BIT IQ 100TQFP |
| AD9956YCPZ | IC SYNTHESIZER 1.8V 48LFCSP |
| S9S08DZ60F1MLH | MCU 60K FLASH MASK AUTO 64-LQFP |
| AD9952YSVZ | IC DDS 14BIT DAC 1.8V 48-TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9911 | 制造商:AD 制造商全称:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
发布紧急采购，3分钟左右您将得到回复。