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| 型号： | AD9910BSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/64页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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Data Sheet
AD9910
Rev. D | Page 25 of 64
REF_CLK
PLL
VCO
SELECT
DIVIDE
CHARGE
PUMP
OUT
IN
PLL_LOOP_FILTER
ENABLE
PLL_LOOP_FILTER
DRV0
CFR3
[29:28]
REFCLK_OUT
XTAL_SEL
REFCLK
INPUT
SELECT
LOGIC
SYSCLK
ICP
CFR3
[21:19]
N
CFR3
[7:1]
VCO SEL
CFR3
[26:24]
÷2
REFCLK
INPUT DIVIDER BYPASS
CFR3[15]
PLL ENABLE
CFR3
[8]
REFCLK
INPUT DIVIDER
RESETB
CFR3[14]
94
95
2
90
91
0
1
0
1
2
7
3
0
1
06479-
013
Figure 30. REF_CLK Block Diagram
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected,
the REF_CLK/REF_CLK pins must be driven by an external
signal source (single-ended or differential). Input frequencies
up to 2 GHz are supported. For input frequencies greater than
1 GHz, the input divider must be enabled for proper operation
of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT has
programmable drive capability. This is controlled by two bits, as
listed in Table 7.
Table 7. REFCLK_OUT Buffer Control
DRV0 Bits (CFR3[29:28])
REFCLK_OUT Buffer
00
Disabled (tristate)
01
Low output current
10
Medium output current
11
High output current
Crystal Driven REF_CLK/REF_CLK
When using a crystal at the REF_CLK/REF_CLK input, the
resonant frequency should be approximately 25 MHz. Figure 31
shows the recommended circuit configuration. The internal
oscillator works with fundamental mode crystals only. Crystal
operation is enabled by a Logic 1 (1.8 V logic required) on the
XTAL_SEL pin.
06479-
014
REF_CLK
39pF
XTAL
90
91
Figure 31. Crystal Connection Diagram
Direct Driven REF_CLK/REF_CLK
When driving the REF_CLK/REF_CLK inputs directly from a
signal source, either single-ended or differential signals can be
used. With a differential signal source, the REF_CLK/REF_CLK
pins are driven with complementary signals and ac-coupled with
0.1 F capacitors. With a single-ended signal source, either a
single-ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 F capacitors are used to ac couple both REF_CLK/
REF_CLK pins to avoid disturbing the internal dc bias voltage
of ~1.35 V. See Figure 32 for more details.
The REF_CLK/REF_CLK input resistance is ~2.5 k differential
(~1.2 k single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/REF_CLK input resistance
is relatively high; therefore, its effect on the termination impedance
is negligible and can usually be chosen to be the same as the
output impedance of the signal source. The bottom two examples
in Figure 32 assume a signal source with a 50 output
impedance.
06479-
015
TERMINATION
REF_CLK
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
90
91
0.1F
PECL,
LVPECL,
OR
LVDS
DRIVER
REF_CLK
90
91
50
0.1F
BALUN
(1:1)
REF_CLK
90
91
0.1F
50
Figure 32. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides the option to use
a reference clock frequency that is significantly lower than the
system clock frequency. The PLL supports a wide range of
programmable frequency multiplication factors (12× to 127×)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9911 | 制造商:AD 制造商全称:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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