参数资料
| 型号： | AD9912ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/40页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS DAC 14BIT 64LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
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AD9912
Rev. F | Page 18 of 40
06
76
3-
0
32
DAC
(14-BIT)
ANGLE TO
AMPLITUDE
CONVERSION
14
19
48
14
PHASE
OFFSET
Q
D
48-BIT ACCUMULATOR
FREQUENCY
TUNING WORD
(FTW)
fS
DAC_RSET
DAC_OUT
DAC_OUTB
DAC I-SET
REGISTERS
AND LOGIC
Figure 40. DDS Block Diagram
The input to the DDS is a 48-bit FTW that provides the accu-
mulator with a seed value. On each cycle of fS, the accumulator
adds the value of the FTW to the running total of its output.
For example, given an FTW = 5, the accumulator increments
the count by 5 sec on each fS cycle. Over time, the accumulator
reaches the upper end of its capacity (248 in this case) and then
rolls over, retaining the excess. The average rate at which the
accumulator rolls over establishes the frequency of the output
sinusoid. The following equation defines the average rollover
rate of the accumulator and establishes the output frequency
(fDDS) of the DDS:
S
DDS
f
FTW
f
=
48
2
Solving this equation for FTW yields
=
S
DDS
f
FTW
48
2
round
For example, given that fS = 1 GHz and fDDS = 19.44 MHz, then
FTW = 5,471,873,547,255 (0x04FA05143BF7).
The relative phase of the sinusoid can be controlled numerically,
as well. This is accomplished using the phase offset function of
the DDS (a programmable 14-bit value (Δphase); see the I/O
Register Map section). The resulting phase offset, ΔΦ (radians),
is given by
Δ
π
=
Δ
14
2
phase
Φ
DIGITAL-TO-ANALOG (DAC) OUTPUT
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog
converter (DAC).
The DAC outputs its signal to two pins driven by a balanced
current source architecture (see the DAC output diagram in
Figure 41). The peak output current derives from a combination
of two factors. The first is a reference current (IDAC_REF) that is
established at the DAC_RSET pin, and the second is a scale
factor that is programmed into the I/O register map.
The value of IDAC_REF is set by connecting a resistor (RDAC_REF)
between the DAC_RSET pin and ground. The DAC_RSET pin
is internally connected to a virtual voltage reference of 1.2 V
nominal, so the reference current can be calculated by
REF
DAC
REF
DAC
R
I
_
2
.
1
=
Note that the recommended value of IDAC_REF is 120 μA, which
leads to a recommended value for RDAC_REF of 10 kΩ.
The scale factor consists of a 10-bit binary number (FSC)
programmed into the DAC full-scale current register in the
I/O register map. The full-scale DAC output current (IDAC_FS)
is given by
+
=
1024
192
72
_
FSC
I
REF
DAC
FS
DAC
Using the recommended value of RDAC_REF, the full-scale DAC
output current can be set with 10-bit granularity over a range of
approximately 8.6 mA to 31.7 mA. 20 mA is the default value.
0
676
3-
0
33
SWITCH
CONTROL
CODE
IFS/2
AVDD3
AVSS
CURRENT
SWITCH
ARRAY
CURRENT
SWITCH
ARRAY
DAC_OUT
DAC_OUTB
INTERNAL
50
INTERNAL
50
IFS/2 + ICODE
IFS/2 – ICODE
IFS
49
51
50
52
Figure 41. DAC Output
RECONSTRUCTION FILTER
The origin of the output clock signal produced by the AD9912
is the combined DDS and DAC. The DAC output signal appears
as a sinusoid sampled at fS. The frequency of the sinusoid is
determined by the frequency tuning word (FTW) that appears
at the input to the DDS. The DAC output is typically passed
through an external reconstruction filter that serves to remove
the artifacts of the sampling process and other spurs outside the
filter bandwidth. If desired, the signal can then be brought back
on-chip to be converted to a square wave that is routed internally
to the output clock driver or the 2× DLL multiplier.
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