参数资料
| 型号： | AD9912ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/40页 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS DAC 14BIT 64LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 1.8V, 3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
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AD9912
Rev. F | Page 5 of 40
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM CLOCK INPUT
System clock inputs should always be ac-
coupled (both single-ended and differential)
SYSCLK PLL Bypassed
Input Capacitance
1.5
pF
Single-ended, each pin
Input Resistance
2.4
2.6
2.9
kΩ
Differential
Internally Generated DC Bias Voltage2
0.93
1.17
1.38
V
Differential Input Voltage Swing
632
mV p-p
Equivalent to 316 mV swing on each leg
SYSCLK PLL Enabled
Input Capacitance
3
pF
Single-ended, each pin
Input Resistance
2.4
2.6
2.9
kΩ
Differential
Internally Generated DC Bias Voltage2
0.93
1.17
1.38
V
Differential Input Voltage Swing
632
mV p-p
Equivalent to 316 mV swing on each leg
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
9
100
Ω
25 MHz, 3.2 mm × 2.5 mm AT cut
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
1080
1280
1480
mV
Output driver static, see Figure 27 for
output swing vs. frequency
Common-Mode Output Voltage2
0.7
0.88
1.06
V
CMOS Output Driver
Output driver static, see Figure 28 and
Figure 29 for output swing vs. frequency
Output Voltage High (VOH)
2.7
V
IOH = 1 mA, Pin 37 = 3.3 V
Output Voltage Low (VOL)
0.4
V
IOL = 1 mA, Pin 37 = 3.3 V
Output Voltage High (VOH)
1.4
V
IOH = 1 mA, Pin 37 = 1.8 V
Output Voltage Low (VOL)
0.4
V
IOL = 1 mA, Pin 37 = 1.8 V
TOTAL POWER DISSIPATION
DDS Only
637
765
mW
Power-on default, except SYSCLK PLL by-
passed and CMOS driver off; SYSCLK = 1 GHz;
HSTL driver off; spur reduction off; fOUT =
200 MHz
DDS with Spur Reduction On
686
823
mW
Same as “DDS Only” case, except both spur
reduction channels on
DDS with HSTL Driver Enabled
657
788
mW
Same as “DDS Only” case, except HSTL driver
enabled
DDS with CMOS Driver Enabled
729
875
mW
Same as “DDS Only” case, except CMOS
driver and S-divider enabled and at 3.3 V;
CMOS fOUT = 50 MHz (S-divider = 4)
DDS with HSTL and CMOS Drivers Enabled
747
897
mW
Same as “DDS Only” case, except both HSTL
and CMOS drivers enabled; S-divider
enabled and set to 4; CMOS fOUT = 50 MHz
DDS with SYSCLK PLL Enabled
648
777
mW
Same as “DDS Only” case, except 25 MHz on
SYCLK input and PLL multiplier = 40
Power-Down Mode
13
16
mW
Using either the power-down and enable
register or the PWRDOWN pin
1 Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.
2 AVSS = 0 V.
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