参数资料
型号: AD9920ABBCZ
厂商: Analog Devices Inc
文件页数: 15/112页
文件大小: 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
标准包装: 1
位数: 12
电压 - 电源,模拟: 1.6 V ~ 2 V
电压 - 电源,数字: 1.6 V ~ 2 V
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 管件
AD9920A
Rev. B | Page 111 of 112
Table 64. Field Registers (Default Values Are Undefined)
Address
Data Bits
Default
Value
Update Type
Name
Description
0x00
[4:0]
X
VD
SEQ0
Selected V-sequence for first region in the field.
[9:5]
X
SEQ1
Selected V-sequence for second region in the field.
[14:10]
X
SEQ2
Selected V-sequence for third region in the field.
[19:15]
X
SEQ3
Selected V-sequence for fourth region in the field.
[24:20]
X
SEQ4
Selected V-sequence for fifth region in the field.
0x01
[4:0]
X
VD
SEQ5
Selected V-sequence for sixth region in the field.
[9:5]
X
SEQ6
Selected V-sequence for seventh region in the field.
[14:10]
X
SEQ7
Selected V-sequence for eighth region in the field.
[19:15]
X
SEQ8
Selected V-sequence for ninth region in the field.
[21:20]
MULT_SWEEP0
Enables multiplier mode and/or sweep mode for Region 0.
0 = multiplier off/sweep off.
1 = multiplier off/sweep on.
2 = multiplier on/sweep off.
3 = multiplier on/sweep on.
[23:22]
MULT_SWEEP1
Enables multiplier mode and/or sweep mode for Region 1.
[25:24]
MULT_SWEEP2
Enables multiplier mode and/or sweep mode for Region 2.
0x02
[12:0]
X
VD
HDLASTLEN
HD last line length. Line length of last line in the field.
[14:13]
X
MULT_SWEEP3
Enables multiplier mode and/or sweep mode for Region 3.
[16:15]
X
MULT_SWEEP4
Enables multiplier mode and/or sweep mode for Region 4.
[18:17]
X
MULT_SWEEP5
Enables multiplier mode and/or sweep mode for Region 5.
[20:19]
X
MULT_SWEEP6
Enables multiplier mode and/or sweep mode for Region 6.
[22:21]
X
MULT_SWEEP7
Enables multiplier mode and/or sweep mode for Region 7.
[24:23]
X
MULT_SWEEP8
Enables multiplier mode and/or sweep mode for Region 8.
[25]
X
HDLASTLEN_13
HD last line length bit [13] when 14-bit H-counter is enabled.
0x03
[12:0]
X
VD
SCP0
V-Sequence Change Position 0.
[25:13]
X
SCP1
V-Sequence Change Position 1.
0x04
[12:0]
X
VD
SCP2
V-Sequence Change Position 2.
[25:13]
X
SCP3
V-Sequence Change Position 3.
0x05
[12:0]
X
VD
SCP4
V-Sequence Change Position 4.
[25:13]
X
SCP5
V-Sequence Change Position 5.
0x06
[12:0]
X
VD
SCP6
V-Sequence Change Position 6.
[25:13]
X
SCP7
V-Sequence Change Position 7.
0x07
[12:0]
X
VD
SCP8
V-Sequence Change Position 8.
[25:13]
X
VDLEN
VD field length (number of lines in the field).
0x08
[12:0]
X
VD
SGACTLINE1
SG Active Line 1.
[25:13]
X
SGACTLINE2
SG Active Line 2. Set to SG Active Line 1 or maximum if not used.
0x09
[23:0]
X
VD
SGMASK
Masking of VSG outputs during SG active line.
0x0A
[12:0]
X
VD
CLPMASKSTART1
CLPOB Mask Region 1 start position. Set to 8191 to disable.
[25:13]
X
CLPMASKEND1
CLPOB Mask Region 1 end position. Set to 0 to disable.
0x0B
[12:0]
X
VD
CLPMASKSTART2
CLPOB Mask Region 2 start position. Set to 8191 to disable.
[25:13]
X
CLPMASKEND2
CLPOB Mask Region 2 end position. Set to 0 to disable.
0x0C
[12:0]
X
VD
CLPMASKSTART3
CLPOB Mask Region 3 start position. Set to 8191 to disable.
[25:13]
X
CLPMASKEND3
CLPOB Mask Region 3 end position. Set to 0 to disable.
0x0D
[12:0]
X
VD
PBLKMASKSTART1
PBLK Mask Region 1 start position. Set to 8191 to disable.
[25:13]
X
PBLKMASKEND1
PBLK Mask Region 1 end position. Set to 0 to disable.
0x0E
[12:0]
X
VD
PBLKMASKSTART2
PBLK Mask Region 2 start position. Set to 8191 to disable.
[25:13]
X
PBLKMASKEND2
PBLK Mask Region 2 end position. Set to 0 to disable.
0x0F
[12:0]
X
VD
PBLKMASKSTART3
PBLK Mask Region 3 start position. Set to 8191 to disable.
[25:13]
X
PBLKMASKEND3
PBLK Mask Region 3 end position. Set to 0 to disable.
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