参数资料
型号: AD9948KCPZ
厂商: Analog Devices Inc
文件页数: 10/28页
文件大小: 0K
描述: IC CCD SIGNAL PROCESSOR 40-LFCSP
标准包装: 1
类型: CCD 信号处理器,10 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP
包装: 托盘
REV. 0
–18–
AD9948
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 1
Figure 12. Clamp and Blanking Sequence Flexibility
Table XV. External HBLK Register Parameters
Register
Length
Range
Description
HBLKDIR
1b
High/Low
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
HBLKPOL
1b
High/Low
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
HBLKEXTMASK
1b
High/Low
External HBLK Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
000
1
2
111
0
3
11
00
01234
5
6
7
8
9
10
11
12
14
15
0
1
2
3
02
3
H-COUNTER
RESET
VD
NOTES
1. INTERNAL H-COUNTER IS RESET SEVEN CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE COINCIDES WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
HD
XX
X
PxGA GAIN
REGISTER
CLI
XX
X
H-COUNTER
(PIXEL COUNTER)
X
Figure 13. H-Counter Synchronization
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD
falling edge. The PxGA steering is synchronized with the reset
of the internal H-Counter (see Figure 13).
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