参数资料
型号: AD9948KCPZ
厂商: Analog Devices Inc
文件页数: 19/28页
文件大小: 0K
描述: IC CCD SIGNAL PROCESSOR 40-LFCSP
标准包装: 1
类型: CCD 信号处理器,10 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP
包装: 托盘
REV. 0
–26–
AD9948
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 24 shows an example CCD layout. The horizontal regis-
ter contains 28 dummy pixels, which will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9948 horizontal signals for this CCD, three
sequences can be used. Figure 25 shows the first sequence, to be
used during vertical blanking. During this time, there are no
valid OB pixels from the sensor, so the CLPOB signal is not
used. PBLK may be enabled during this time, because no valid
data is available.
Figure 26 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9948.
Figure 27 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
V
H
USE SEQUENCE 2
USE SEQUENCE 3
SEQUENCE 2 (OPTIONAL)
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 24. Example CCD Configuration
VERTICAL SHIFT
VERT SHIFT
SEQUENCE 1: VERTICAL BLANKING
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
DUMMY
INVALID PIXELS
INVALID PIX
Figure 25. Horizontal Sequence during Vertical Blanking
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