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| 型号： | AD9954YSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/40页 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9954/PCBZ-ND - BOARD EVAL FOR 9954 |
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AD9954
Rev. B | Page 20 of 40
The last method in which the sweep ramp rate timer can be
reset is changing from inactive linear sweep mode to active
linear sweep mode using the linear sweep enable bit (CFR1<21>).
For methods two and three, the ramp rate timer loads a value
determined by the state of PS0 (0 = FSRRW, 1 = RSRRW).
Power-Down Functions of the AD9954
The AD9954 supports an externally controlled (or hardware)
power-down feature as well as software-programmable power-
down bits capable of individually powering down specific unused
circuit blocks.
Software-controlled power-down enables individual powering
down of the DAC, comparator, PLL, input clock circuitry, and
the digital logic (CFR1<7:4>). With the exception of CFR1<6>,
these bits are superseded when the externally controlled power-
down pin (PWRDWNCTL) is high. External power-down
control is supported on the AD9954 via the PWRDWNCTL
input pin. When the PWRDWNCTL input pin is high, the
AD9954 enters a power-down mode based on the CFR1<3> bit.
When the PWRDWNCTL input pin is low, it operates normally.
See CFR1<3> in Table 12 for details.
Table 9 details the logic level for each power-down bit that
drives out of the AD9954 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Table 9. Power-Down Control Functions
Control
Mode Active
Description
PWRDWNCTL = 0, CFR1<3> don’t care
Software control
Digital power-down = CFR1<7>
Comparator power-down = CFR1<6>
DAC power-down = CFR1<5>
Clock input power-down = CFR1<4>
PWRDWNCTL = 1, CFR1<3> = 0
External control, fast recovery
power-down mode
Digital power-down = 1’b1
Comparator power-down = 1’b0 or CFR1<6>
DAC power-down = 1’b0
Clock input power-down = 1’b0
PWRDWNCTL = 1, CFR1<3> = 1
External control, full power-down
mode
Digital power-down = 1’b1
Comparator power-down = 1’b1
DAC power-down = 1’b1
Clock input power-down = 1’b1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9955KS6 | 制造商:AD 功能描述:* |
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