- 您现在的位置：买卖IC网 > PDF目录11768 > AD9983AKCPZ-140 (Analog Devices Inc)IC INTRFACE 8BIT 140MSPS 64LFCSP PDF资料下载
参数资料
| 型号： | AD9983AKCPZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/44页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE 8BIT 140MSPS 64LFCSP |
| 标准包装： | 1 |
| 应用： | 视频 |
| 接口： | 模拟 |
| 电源电压： | 1.7 V ~ 3.47 V |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD9983A
Rev. 0 | Page 33 of 44
0x19—Bits[7:0] Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally, at a position established by
the clamp placement register (Register 0x19) and for a duration
set by the clamp duration register (Register 0x1A). Clamping is
started a clamp placement count(Register 0x19) of pixel periods
after the trailing edge of Hsync. The clamp placement may be
programmed to any value between 1 and 255. A value of 0 is not
supported.
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between Hsync and the image. When EXTCLMP = 1,
this register is ignored. Power-up default setting is 8.
0x1A—Bits[7:0] Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally at a position established by
the clamp placement register (and for a duration set by the
clamp duration register). Clamping begins a clamp placement
count (Register 0x19) of pixel periods after the trailing edge of
Hsync. The clamp duration may be programmed to any value
between 1 and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen, and a slow
recovery from large changes in the average picture level (APL),
or bright-ness. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 20 DDR.
0x1B—Bit[7] Clamp Polarity Override
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The power-up
default setting is 0.
Table 37. Clamp Polarity Override Settings
Override Bit
Result
0
Clamp polarity determined by chip
1
Clamp polarity determined by user
Register 0x1B, Bit 6
0x1B—Bit[6] Clamp Input Polarity
This bit indicates the polarity of the clamp signal only if Bit 7 of
Register 0x1B = 1. The power-up default setting is 1.
Table 38. Clamp Polarity Override Settings
Value
Result
0
Active low external clamp
1
Active high external clamp
0x1B—Bit[5] Auto-Offset Enable
This bit selects between auto-offset mode and manual offset
mode (auto-offset disabled) (See the section on auto-offset
operation). The power-up default setting is 0.
Table 39. Auto-Offset Settings
Auto-Offset
Result
0
Auto-offset is disabled
1
Auto-offset is enabled (manual offset mode)
0x1B—Bits[4:3] Auto-Offset Update Frequency
These bits control how often the auto-offset circuit is updated
(if enabled). Updating every 64 Hsyncs is recommended. The
power-up default setting is 11.
Table 40. Auto-Offset Update Mode
Clamp Update
Result
00
Update offset every clamp period
01
Update offset every 16 clamp periods
10
Update offset every 64 clamp periods
11
Update offset every Vsync periods
0x1B—Bits[2:0]
Must be written to 011 for proper operation.
SOG CONTROL
0x1D—Bits[7:3] SOG Slicer Threshold
This register allows the comparator threshold of the SOG slicer
to be adjusted. This register adjusts it in steps of 8 mV, with the
minimum setting equaling 8 mV and the maximum setting
equaling 256 mV. The power-up default setting is 15 DDR and
corresponds to a threshold value of 128 mV.
0x1D—Bit[2] SOGOUT Polarity
This bit sets the polarity of the SOGOUT signal. The power-up
default setting is 0.
Table 41. SOGOUT Polarity Settings
SOGOUT
Result
0
Active low
1
Active high
0x1D—Bits[1:0] SOGOUT Select
These register bits control what is output on the SOGOUT pin.
Options are the raw SOG from the slicer (this is the
unprocessed SOG signal produced from the sync slicer), the
raw Hsync, the regenerated sync from the sync filter, which can
generate missing syncs either due to coasting or drop-out, or
finally the filtered sync which excludes extraneous syncs not
occurring within the sync filter window. The power-up default
setting is 0.
Table 42. SOGOUT Select
SOGOUT Select
Function
00
Raw SOG from sync slicer (SOGIN0 or SOGIN1)
01
Raw Hsync (HSYNC0 or HSYNC1)
10
Regenerated Hsync from sync filter
11
Filtered Hsync from sync filter
相关PDF资料 |
PDF描述 |
|---|---|
| V150B24H150BG | CONVERTER MOD DC/DC 24V 150W |
| 5227079-5 | CONN PLUG BNC RG58 CRIMP AU |
| VE-JTM-IW-F1 | CONVERTER MOD DC/DC 10V 100W |
| VE-JT1-IW-F4 | CONVERTER MOD DC/DC 12V 100W |
| MS27474E14B35SD | CONN RCPT 37POS JAM NUT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9983AKCPZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKCPZ-170 | 功能描述:IC INTRFACE 8BIT 170MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9983AKCPZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKSTZ-140 | 功能描述:IC DISPLAY 8BIT 140MSPS 80LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9983AKSTZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
发布紧急采购，3分钟左右您将得到回复。