ADA4940-1/ADA4940-2
Data Sheet
Rev. C | Page 26 of 32
INPUT AND OUTPUT CAPACITIVE AC COUPLING
coupled applications, it is nonetheless possible to use it in ac-
coupled circuits. Input ac coupling capacitors can be inserted
between the source and RG. This ac coupling blocks the flow
of the dc common-mode feedback current and causes the
equal the dc output common-mode voltage. These ac coupling
capacitors must be placed in both loops to keep the feedback
factors matched. Output ac coupling capacitors can be placed in
series between each output and its respective load.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
biased at a voltage approximately equal to the midsupply point,
[(+VS) + (VS)]/2. Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (10 k or greater resistors), be used. The output
that the VOCM input is driven by a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 250 k.
DISABLE PIN
be used to minimize the quiescent current consumed when the
device is not being used. DISABLE is asserted by applying a low
logic level to the DISABLE pin. The threshold between high and
low logic levels is nominally 1.4 V above the negative supply rail.
The DISABLE pin features an internal pull-up network that
enables the amplifier for normal operation. The
ADA4940-1/ADA4940-2 DISABLE pin can be left floating (that is, no
external connection is required) and does not require an
external pull-up resistor to ensure normal on operation (see
output is high impedance. Note that the outputs are tied to the
inputs through the feedback resistors and to the source using the
gain resistors. In addition, there are back-to-back diodes on the
input pins that limit the differential voltage to 1.2 V.
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063
DISABLE
AMPLIFIER
BIAS CURRENT
–VS
+VS
Figure 70. DISABLE Pin Circuit
DRIVING A CAPACITIVE LOAD
A purely capacitive load reacts with the bond wire and pin
frequency ringing in the transient response and loss of phase
margin. One way to minimize this effect is to place a resistor in
series with each output to buffer the load capacitance. The resistor
and load capacitance form a first-order, low-pass filter; therefore,
the resistor value should be as small as possible. In some cases,
the ADCs require small series resistors to be added on their inputs.
Figure 71 illustrates the capacitive load vs. the series resistance
required to maintain a minimum 45° of phase margin.
120
0
5
100
10
1000
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064
20
40
60
80
100
SER
IES
R
ESI
ST
A
N
C
E
(
)
LOAD CAPACITANCE (pF)
+IN
–OUT
+OUT
–FB
+FB
–IN
VOCM
0.1F
RS
RS
R1
CL
R2
R4
+2.5V
–2.5V
R3
VIN
Figure 71. Capacitive Load vs. Series Resistance (LFSCP)